參數(shù)資料
型號(hào)： EDI2DL32256V38BC
英文描述： 256Kx32 Synchronous Pipline Burst SRAM 3.3V(3.3V,3.8ns,256Kx32同步流水線脈沖靜態(tài)RAM)
中文描述： 256Kx32同步管材突發(fā)SRAM的3.3（3.3伏，3.8ns，256Kx32同步流水線脈沖靜態(tài)內(nèi)存）
文件頁(yè)數(shù)： 1/8頁(yè)
文件大?。?/td> 96K
代理商： EDI2DL32256V38BC
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
November 2000, Rev. 1
ECO #13417
EDI2DL32256V
DESCRIPTION
The EDI2DL32256VxxBC is a 3.3V, 256Kx32 Synchronous Pipeline
Burst SRAM constructed with two 256Kx16 die mounted on a
multi-layer laminate substrate. The device is packaged in a 119
lead, 14mm by 22mm, BGA. It is available with clock speeds of166,
150 and 133 MHz. The device is a Pipeline Burst SRAM, allowing
the user to develop a fast external memory for Texas Instruments’
“C6x”. In Burst Mode data from the first memory location is
available in three clock cycles, while the subsequent data is
available in one clock cycle (3/1/1/1). Subsequent burst ad-
dresses are generated by the TMS320C6x DSP. Individual address
locations can also be read, allowing one memory access in 3 clock
cycles. All synchronous inputs are gated by registers controlled by
a positive-edge-triggered clock input (CLK). The synchronous in-
puts include all addresses, all data inputs, chip enable (CE\), burst
control input (ADSC\), byte write enables (BW0\ to BW3\) and
Write Enable (BWE\).
Asynchronous inputs include the output enable (OE\), burst mode
control (MODE), and sleep mode control (ZZ). The data outputs
(DQ), enabled by OE\, are also asynchronous.
Address lines and the chip enable are registered with the address
status controller (ADSC\) input pin.
256Kx32 Synchronous Pipline Burst SRAM 3.3V
FEATURES
s tKHQV times of 3.5, 3.8 and 4.0ns
s 166, 150 and 133 MHz clock speed
s DSP Memory Solution
Texas Instruments’ TMS320C6201
Texas Instruments’ TMS320C67x
s Package:
119 pin BGA, JEDEC MO-163
s 3.3V Operating Supply Voltage
s 3.5ns Output Enable access time
s Single Write Control and Output Enable Lines
s Single Chip Enable Line
s 56% space savings vs. monolithic TQFPs
s Multiple VCC and VSS pins
s Reduced inductance and capacitance
BLOCK DIAGRAM
FIG. 1
12
3
4
5
6
7
A
VDD
AA
NC
A
VDD
A
B
NC
A
ADSC\
A
NC
B
C
NC
A
VDD
AA
NC
C
D
DQ16
NC
VSS
NC
VSS
NC
DQ8
D
E
DQ18
DQ17
VSS
CE\
VSS
DQ9
DQ10
E
F
VDD
DQ19
VSS
OE\
VSS
DQ11
VDD
F
G
DQ21
DQ20
BE2\NC
BE1\DQ12
DQ13
G
H
DQ23
DQ22
VSS
NC
VSS
DQ14
DQ15
H
J
VDD
NC
VDD
NC
VDD
J
K
DQ31
DQ30
VSS
CLK
VSS
DQ6
DQ7
K
L
DQ29
DQ28
BE3\NC
BE0\DQ4
DQ5
L
M
VDD
DQ27
VSS
BWE\
VSS
DQ3
VDD
M
N
DQ26
DQ25
VSS
A1
VSS
DQ1
DQ2
N
P
DQ24
NC
VSS
A0
VSS
NC
DQ0
P
R
NC
A
MODE
VDD
NC
A
NC
R
T
NC
A
NC
ZZ
T
U
VDD
NC
VDD
U
1
2345
6
7
PIN CONFIGURATION
A0-17
CLK
ADSC\
OE\
BWE\
CE\
MODE
ZZ
BE0\
BE1\
BE2\
BE3\
256K X 16
SSRAM
256K X 16
SSRAM
DQ0-7
DQ8-15
DQ16-23
DQ24-31
相關(guān)PDF資料
PDF描述
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