- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄97875 > EDI2AG27265V85D1 2x64Kx72, 3.3V,8.5ns, Sync/Sync Burst SRAM Module(2x64Kx72, 3.3V，8.5ns,同步/同步脈沖靜態(tài)RAM模塊) PDF資料下載
參數(shù)資料
| 型號： | EDI2AG27265V85D1 |
| 英文描述： | 2x64Kx72, 3.3V,8.5ns, Sync/Sync Burst SRAM Module(2x64Kx72, 3.3V，8.5ns,同步/同步脈沖靜態(tài)RAM模塊) |
| 中文描述： | 2x64Kx72，3.3伏，8.5ns，同步/同步突發(fā)靜態(tài)存儲器模塊（2x64Kx72，3.3伏，8.5ns，同步/同步脈沖靜態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 2802K |
| 代理商： | EDI2AG27265V85D1 |
4
White Electronic Designs Corporation Westborough, MA 01581
(508) 366-5151 www.whiteedc.com
EDI2AG27265V
July 1999 Rev
ECO
PIN DESCRIPTIONS
DIMM Pins
Symbol
Type
Description
3, 6, 7, 10, 11
A0-A17
Input
Addresses: These inputs are registered and must meet the setup and hold
14, 15, 18, 19, 20
Synchronous times around the rising edge of CLK. The burst counter generates internal
17, 16, 13, 12, 98
addresses associated with A0 and A1, during burst and wait cycle.
33, 47, 61
BW1\, BW2\,
Input
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ
75, 89, 103
BW3\, BW4\, Synchronous cycle. BW0/ controls DQ0-7 and DQP0, BW1\ controls DQ8-15 and DQP1.
117,13
BW5\, BW6\,
BW2\ controls DQ16-23 and DQP2. BW3\ controls DQ24-31 and DQP3.
BW7\, BW8\
BW4\ controls DQ32-39 and DQP4. BW5\ controls DQ40-47 and DQP5.
BW6\ controls DQ48-55 and DQP6. BW7\ controls DQ56-64 and DQP7.
32
BWE\
Input
Write Enable: This active LOW input gates byte write operations and must
Synchronous
meet the setup and hold times around the rising edge of CLK.
25
GW\
Input
Global Write: This active LOW input allows a full 72-bit WRITE to occur
Synchronous
independent of the BWE\ and BWx\ lines and must meet the setup and hold
times around the rising edge of CLK.
30
CLK
Input
Clock: This signal registers the addresses, data, chip enables, write control
Synchronous
and burst control inputs on its rising edge. All synchronous inputs must
meet setup and hold times around the clock’s rising edge.
29, 31,
E1\, E2\
Input
Bank Enables: These active LOW inputs are used to enable each
E3\, E4\
Synchronous
individual bank and to gate ADSP\.
23
G\
Input
Output Enable: This active LOW asynchronous input enables the data output
drivers.
26
ADV\
Input
Address Status Processor: This active LOW input is used to control the
Synchronous
internal burst counter. A HIGH on this pin generates wait cycle (no address
advance).
27
ADSP\
Input
Address Status Processor: This active LOW input, along with EL\ and EH\
Synchronous
being LOW, causes a new external address to be registered and a READ
cycle is initiated using the new address.
28
ADSC\
Input
Address Status Controller: This active LOW input causes device to be de-
Synchronous
selected or selected along with new external address to be registered. A
READ or WRITE cycle is initiated depending upon write control inputs.
Various
DQ0-63
Input/Output
Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is
DQ16-23, fourth byte is DQ24-31, fifth byte is DQ32-39, sixth byte is
DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64.
38, 48, 62
DQP0-7
Input/Output
Parity Inputs/Outputs: DQP0 is parity bit for DQ0-7. DQP1 is parity bit for DQ8-15.
76, 90, 104
DQP2 is parity bit for DQ16-23. DQP3 is parity bit for DQ24-31. DQP4\ is parity
118,132
bit for DQ32-39. DQP5 is parity bit for DQ40-47. DQP6\ is parity bit for DQ48-55.
DQP7isparitybitforDQ56-64andDQP7.InordertousethedeviceConfigured
as a128K x 64, the parity bits need to be tied to Vss through a 10K ohm resistor.
Various
Vcc
Supply
Corepowersupply:+3.3V-5%/+10%
Various
Vss
Ground
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDI2AG27265V9D1 | 2x64Kx72, 3.3V,9ns, Sync/Sync Burst SRAM Module(2x64Kx72, 3.3V，9ns,同步/同步脈沖靜態(tài)RAM模塊) |
| EDI2CG272128V-D1 | SSRAM Modules |
| EDI2CG472128V-D2 | SSRAM Modules |
| EDI2CG472256V-D2 | SSRAM Modules |
| EDI2CG272128V12D1 | 2x128Kx72, 3.3V S nc/S nc Burst Flow-Through(2x128Kx72, 3.3V，12ns,同步/同步脈沖靜態(tài)RAM模塊(流通結(jié)構(gòu)）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDI2CG272128V | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM |
| EDI2CG272128V12D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM |
| EDI2CG272128V15D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM |
| EDI2CG272128V85D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM |
| EDI2CG272128V9D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。