- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄97875 > EDI2AG27265V12D1 2x64Kx72, 3.3V,12ns, Sync/Sync Burst SRAM Module(2x64Kx72, 3.3V，12ns,同步/同步脈沖靜態(tài)RAM模塊) PDF資料下載
參數(shù)資料
| 型號： | EDI2AG27265V12D1 |
| 英文描述： | 2x64Kx72, 3.3V,12ns, Sync/Sync Burst SRAM Module(2x64Kx72, 3.3V，12ns,同步/同步脈沖靜態(tài)RAM模塊) |
| 中文描述： | 2x64Kx72，3.3伏，12ns，同步/同步突發(fā)靜態(tài)存儲器模塊（2x64Kx72，3.3伏，12ns，同步/同步脈沖靜態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 2802K |
| 代理商： | EDI2AG27265V12D1 |
5
EDI2AG27265V
White Electronic Designs Corporation Westborough, MA 01581
(508) 366-5151 www.whiteedc.com
July1999 Rev
ECO
SYNCHRONOUS BURST - TRUTH TABLE
Operation
E1\ E2\ ADSP\
ADSC\ ADV\ GW\ G\ CLK
DQ Addr. Used
Deselected Cycle, Power Down; Bank 1H X
X
L
X
X L-H
High-Z
None
Deselected Cycle, Power Down; Bank 2X H
X
L
X
X L-H
High-Z
None
Read Cycle, Begin Burst; Bank 1
L
H
L
X
L L-H
Q
External
Read Cycle, Begin Burst; Bank 1
L
H
L
X
H L-H
High-Z External
Read Cycle, Begin Burst; Bank 2
H
L
X
L L-H
Q
External
Read Cycle, Begin Burst; Bank 2
H
L
X
H L-H
High-Z External
Write Cycle, Begin Burst; Bank 1
L
H
L
X
L
X L-H
D
External
Write Cycle, Begin Burst; Bank 2
H
L
H
L
X
L
X L-H
D
External
Read Cycle, Begin Burst; Bank 1
L
H
L
X
H
L L-H
Q
External
Read Cycle, Begin Burst; Bank 1
L
H
L
X
H
H L-H
High-Z External
Read Cycle, Begin Burst; Bank 2
H
L
H
L
X
H
L L-H
Q
External
Read Cycle, Begin Burst; Bank 2
H
L
H
L
X
H
H L-H
High-Z External
Read Cycle, Continue Burst; Bank 1
X
H
X
H
L
H
L L-H
Q
Next
Read Cycle, Continue Burst; Bank 1
X
H
X
H
L
H
H L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 2
H
X
H
L
H
L L-H
Q
Next
Read Cycle, Continue Burst; Bank 2
H
X
H
L
H
H L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 1
H
X
H
L
H
L L-H
Q
Next
Read Cycle, Continue Burst; Bank 1
H
X
H
L
H
H L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 2
H
X
H
L
H
L L-H
Q
Next
Read Cycle, Continue Burst; Bank 2
H
X
H
L
H
H L-H
High-Z
Next
Write Cycle, Continue Burst; Bank 1
X
H
L
X L-H
D
Next
Write Cycle, Continue Burst; Bank 1
H
X
H
L
X L-H
D
Next
Write Cycle, Continue Burst; Bank 2
H
X
H
L
X L-H
D
Next
Write Cycle, Continue Burst; Bank 2
H
X
H
L
X L-H
D
Next
Read Cycle, Suspend Burst; Bank 1
X
H
L L-H
Q
Current
Read Cycle, Suspend Burst; Bank 1
X
H
H L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 2
H
X
H
L L-H
Q
Current
Read Cycle, Suspend Burst; Bank 2
H
X
H
H L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 1
H
X
H
L L-H
Q
Current
Read Cycle, Suspend Burst; Bank 1
H
X
H
H L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 2
H
X
H
L L-H
Q
Current
Read Cycle, Suspend Burst; Bank 2
H
X
H
H L-H
High-Z
Current
Write Cycle, Suspend Burst; Bank 1
X
H
L
X L-H
D
Current
Write Cycle, Suspend Burst; Bank 1
H
X
H
L
X L-H
D
Current
Write Cycle, Suspend Burst; Bank 2
H
X
H
L
X L-H
D
Current
Write Cycle, Suspend Burst; Bank 2
H
X
H
L
X L-H
D
Current
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDI2AG27265V85D1 | 2x64Kx72, 3.3V,8.5ns, Sync/Sync Burst SRAM Module(2x64Kx72, 3.3V，8.5ns,同步/同步脈沖靜態(tài)RAM模塊) |
| EDI2AG27265V9D1 | 2x64Kx72, 3.3V,9ns, Sync/Sync Burst SRAM Module(2x64Kx72, 3.3V，9ns,同步/同步脈沖靜態(tài)RAM模塊) |
| EDI2CG272128V-D1 | SSRAM Modules |
| EDI2CG472128V-D2 | SSRAM Modules |
| EDI2CG472256V-D2 | SSRAM Modules |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDI2CG272128V | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM |
| EDI2CG272128V12D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM |
| EDI2CG272128V15D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM |
| EDI2CG272128V85D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM |
| EDI2CG272128V9D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。