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參數(shù)資料
| 型號： | EBE52UD6ABSA |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 512MB DDR2 SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks) |
| 中文描述： | 512MB的DDR2 SDRAM內(nèi)存的SO - DIMM（6400字× 64位，2個等級） |
| 文件頁數(shù)： | 1/23頁 |
| 文件大?。?/td> | 254K |
| 代理商： | EBE52UD6ABSA |
Document No. E0722E30 (Ver. 3.0)
Date Published July 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005
DATA SHEET
512MB DDR2 SDRAM SO-DIMM
EBE52UD6AFSA
(64M words
×
64 bits, 2 Ranks)
Description
The EBE52UD6AFSA is 64M words
×
64 bits, 2 ranks
DDR2 SDRAM Small Outline Dual In-line Memory
Module, mounting 8 pieces of 512M bits DDR2
SDRAM sealed in FBGA (
μ
BGA
) package. Read and
write operations are performed at the cross points of
the CK and the /CK. This high-speed data transfer is
realized by the 4 bits prefetch-pipelined architecture.
Data strobe (DQS and /DQS) both for read and write
are available for high speed and reliable data bus
design. By setting extended mode register, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
This module provides high density mounting without
utilizing surface mount technology. Decoupling
capacitors are mounted beside each FBGA (
μ
BGA) on
the module board.
Note: Do not push the components or drop the
modules in order to avoid mechanical defects,
which may result in electrical defects.
Features
200-pin socket type small outline dual in line memory
module (SO-DIMM)
PCB height: 30.0mm
Lead pitch: 0.6mm
Lead-free (RoHS compliant)
Power supply: VDD
=
1.8V
±
0.1V
Data rate: 667Mbps/533Mbps/400Mbps (max.)
SSTL_18 compatible I/O
Double-data-rate architecture: two data transfers per
clock cycle
Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
Four internal banks for concurrent operation
(Components)
Data mask (DM) for write data
Burst lengths: 4, 8
/CAS Latency (CL): 3, 4, 5
Auto precharge operation for each burst access
Auto refresh and self refresh modes
Average refresh period
7.8
μ
s at 0
°
C
≤
TC
≤
+
85
°
C
3.9
μ
s at
+
85
°
C
<
TC
≤
+
95
°
C
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
/DQS can be disabled for single-ended Data Strobe
operation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EBE52UD6ABSA-4A-E | 512MB DDR2 SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks) |
| EBE52UD6ABSA-5C-E | 512MB DDR2 SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks) |
| EBE52UD6AFSA-4A-E | 512MB DDR2 SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks) |
| EBE52UD6AFSA-5C-E | 512MB DDR2 SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks) |
| EBE52UD6AFSA-6E-E | 512MB DDR2 SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EBE52UD6ABSA-4A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB DDR2 SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks) |
| EBE52UD6ABSA-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB DDR2 SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks) |
| EBE52UD6AFSA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB DDR2 SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks) |
| EBE52UD6AFSA-4A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB DDR2 SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks) |
| EBE52UD6AFSA-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB DDR2 SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks) |
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