參數(shù)資料
型號(hào): EBE51RD8ABFA
廠商: Elpida Memory, Inc.
英文描述: 512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
中文描述: 512MB的注冊(cè)DDR2 SDRAM DIMM內(nèi)存(6400字× 72位,1個(gè)等級(jí))
文件頁(yè)數(shù): 16/22頁(yè)
文件大小: 190K
代理商: EBE51RD8ABFA
EBE51RD8AEFA
Data Sheet E0645E30 (Ver. 3.0)
16
-5C
-4A
Frequency (Mbps)
533
400
Parameter
Symbol
min.
max.
min.
max.
Unit
Notes
Active bank A to active bank B command
period
Write recovery time
Auto precharge write recovery + precharge
time
Internal write to read command delay
tRRD
7.5
7.5
ns
tWR
15
(tWR/tCK)+
(tRP/tCK)
7.5
15
(tWR/tCK)+
(tRP/tCK)
10
ns
tDAL
tCK
1
tWTR
ns
Internal read to precharge command delay
tRTP
7.5
7.5
ns
Exit self refresh to a non-read command
tXSNR
tRFC + 10
tRFC + 10
ns
Exit self refresh to a read command
Exit precharge power down to any non-read
command
Exit active power down to read command
Exit active power down to read command
(slow exit/low power mode)
CKE minimum pulse width (high and low
pulse width)
Output impedance test driver delay
Auto refresh to active/auto refresh command
time
Average periodic refresh interval
(0
°
C
TC
+85
°
C)
tXSRD
200
200
tCK
tXP
2
2
tCK
tXARD
2
2
tCK
3
tXARDS
6
AL
6
AL
tCK
2, 3
tCKE
3
3
tCK
tOIT
0
12
0
12
ns
tRFC
105
105
ns
tREFI
7.8
7.8
μ
s
(+85
°
C
<
TC
+95
°
C)
tREFI
3.9
3.9
μ
s
Minimum time clocks remains ON after CKE
asynchronously drops low
Notes: 1. For each of the terms above, if not already an integer, round to the next higher integer.
2. AL: Additive Latency.
3. MRS A12 bit defines which active power down exit timing to be applied.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test.
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test.
tDELAY
tIS + tCK +
tIH
tIS + tCK +
tIH
ns
DQS
/DQS
tDS
tDH
tDS
tDH
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
CK
/CK
tIS
tIH
tIS
tIH
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
Input Waveform Timing 1 (tDS, tDH)
Input Waveform Timing 2 (tIS, tIH)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EBE51RD8ABFA-4A-E 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51RD8ABFA-5C-E 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51RD8AEFA 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51RD8AEFA-4A-E 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51RD8AEFA-5C-E 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)