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參數(shù)資料
| 型號： | EBE51ED8AGFA-4A-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank) |
| 中文描述： | 64M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 |
| 封裝： | ROHS COMPLIANT, DIMM-240 |
| 文件頁數(shù)： | 16/22頁 |
| 文件大小： | 186K |
| 代理商： | EBE51ED8AGFA-4A-E |
EBE51ED8AEFA
Data Sheet E0585E20 (Ver. 2.0)
16
-5C
-4A
Frequency (Mbps)
533
400
Parameter
Symbol
min.
max.
min.
max.
Unit
Notes
Active bank A to active bank B command
period
Write recovery time
Auto precharge write recovery + precharge
time
Internal write to read command delay
tRRD
7.5
7.5
ns
tWR
15
(tWR/tCK)+
(tRP/tCK)
7.5
15
(tWR/tCK)+
(tRP/tCK)
10
ns
tDAL
tCK
1
tWTR
ns
Internal read to precharge command delay
tRTP
7.5
7.5
ns
Exit self refresh to a non-read command
tXSNR
tRFC + 10
tRFC + 10
ns
Exit self refresh to a read command
Exit precharge power down to any non-read
command
Exit active power down to read command
Exit active power down to read command
(slow exit/low power mode)
CKE minimum pulse width (high and low
pulse width)
Output impedance test driver delay
Auto refresh to active/auto refresh command
time
Average periodic refresh interval
Minimum time clocks remains ON after CKE
asynchronously drops low
Notes: 1. For each of the terms above, if not already an integer, round to the next higher integer.
2. AL: Additive Latency.
3. MRS A12 bit defines which active power down exit timing to be applied.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test.
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test.
tXSRD
200
200
tCK
tXP
2
2
tCK
tXARD
2
2
tCK
3
tXARDS
6
AL
6
AL
tCK
2, 3
tCKE
3
3
tCK
tOIT
0
12
0
12
ns
tRFC
105
105
ns
tREFI
tIS + tCK +
tIH
7.8
tIS + tCK +
tIH
7.8
μ
s
tDELAY
ns
DQS
/DQS
tDS
tDH
tDS
tDH
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
CK
/CK
tIS
tIH
tIS
tIH
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
Input Waveform Timing 1 (tDS, tDH)
Input Waveform Timing 2 (tIS, tIH)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EBE51ED8AGFA-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank) |
| EBE51ED8AGFA-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank) |
| EBE51ED8AGWA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR2 SDRAM DIMM |
| EBE51ED8AGWA-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR2 SDRAM DIMM |
| EBE51ED8AGWA-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR2 SDRAM DIMM |
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