參數(shù)資料
型號(hào): EBE21RD4AEFA
廠商: Elpida Memory, Inc.
元件分類: 圓形連接器
英文描述: Circular Connector; No. of Contacts:12; Series:MS27466; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:15-97 RoHS Compliant: No
中文描述: 2GB的注冊(cè)DDR2 SDRAM DIMM內(nèi)存(256M字× 72位,2個(gè)等級(jí))
文件頁數(shù): 12/22頁
文件大?。?/td> 173K
代理商: EBE21RD4AEFA
EBE21RD4ABHA
Data Sheet E0451E20 (Ver. 2.0)
12
Parameter
Symbol Grade
max
Unit
Test condition
-5C
6330
Auto-refresh current
IDD5
-4A
5830
mA
tCK = tCK (IDD);
Refresh command at every tRFC (IDD) interval;
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self Refresh Mode;
CK and /CK at 0V;
CKE
0.2V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
all bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD (IDD)
1
×
tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),
tRCD = 1
×
tCK (IDD);
CKE is H, CS is H between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4W;
Self-refresh current
IDD6
320
mA
-5C
8250
Operating current
(Bank interleaving)
IDD7
-4A
7480
mA
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD
values must be met with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN
VIL (AC) (max.)
H is defined as VIN
VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-533
DDR2-400
Parameter
4-4-4
3-3-3
Unit
CL(IDD)
4
3
tCK
tRCD(IDD)
15
15
ns
tRC(IDD)
55
55
ns
tRRD(IDD)
7.5
7.5
ns
tCK(IDD)
3.75
5
ns
tRAS(min.)(IDD)
40
40
ns
tRAS(max.)(IDD)
70000
70000
ns
tRP(IDD)
15
15
ns
tRFC(IDD)
105
105
ns
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EBE21RD4AEFA-4A-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)
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