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參數(shù)資料
| 型號： | EBE11ED8AGFA-5C-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 72 bits, 2 Ranks) |
| 中文描述： | 128M X 72 DDR DRAM MODULE, 0.5 ns, DMA240 |
| 封裝： | ROHS COMPLIANT, DIMM-240 |
| 文件頁數(shù)： | 12/22頁 |
| 文件大?。?/td> | 175K |
| 代理商： | EBE11ED8AGFA-5C-E |
EBE11ED8ABFA
Data Sheet E0379E40 (Ver. 4.0)
12
Parameter
Symbol Grade
max.
Unit
Test condition
Self Refresh Mode;
CK and /CK at 0V;
CKE
≤
0.2V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
all bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD (IDD)
1
×
tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),
tRCD = 1
×
tCK (IDD);
CKE is H, CS is H between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4W;
Self-refresh current
IDD6
108
mA
Operating current
(Bank interleaving)
(Another rank is in IDD2P)
IDD7
-5C
-4A
2970
2772
mA
Operating current
(Bank interleaving)
(Another rank is in IDD3N)
IDD7
-5C
-4A
3465
3240
mA
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD
values must be met with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN
≤
VIL (AC) (max.)
H is defined as VIN
≥
VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-533
DDR2-400
Parameter
4-4-4
3-3-3
Unit
CL(IDD)
4
3
tCK
tRCD(IDD)
15
15
ns
tRC(IDD)
55
55
ns
tRRD(IDD)
7.5
7.5
ns
tCK(IDD)
3.75
5
ns
tRAS(min.)(IDD)
40
40
ns
tRAS(max.)(IDD)
70000
70000
ns
tRP(IDD)
15
15
ns
tRFC(IDD)
105
105
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EBE11ED8AGFA-6E-E | 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 72 bits, 2 Ranks) |
| EBE11ED8ABFA-5C-E | 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 72 bits, 2 Ranks) |
| EBE11ED8AEFA | Circular Connector; No. of Contacts:5; Series:MS27466; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No |
| EBE11ED8AEFA-4A-E | Circular Connector; No. of Contacts:37; Series:MS27466; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No |
| EBE11ED8AGFA | LJT 24C 12#16 12#12 PIN PLUG |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EBE11ED8AGFA-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Unbuffered DDR2 SDRAM DIMM (128M words x 72 bits, 2 Ranks) |
| EBE11ED8AGWA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Unbuffered DDR2 SDRAM DIMM |
| EBE11ED8AGWA-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Unbuffered DDR2 SDRAM DIMM |
| EBE11ED8AGWA-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Unbuffered DDR2 SDRAM DIMM |
| EBE11ED8AJWA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Unbuffered DDR2 SDRAM DIMM |
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