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參數(shù)資料
| 型號(hào)： | EBD11ED8ABFB |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 1GB Unbuffered DDR SDRAM DIMM EBD11ED8ABFB (128M words 】 72 bits, 2 Banks) |
| 中文描述： | 1GB的無(wú)緩沖DDR SDRAM的內(nèi)存EBD11ED8ABFB（128M的關(guān)鍵詞】72位，2組） |
| 文件頁(yè)數(shù)： | 1/19頁(yè) |
| 文件大?。?/td> | 209K |
| 代理商： | EBD11ED8ABFB |
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Document No. E0295E20 (Ver. 2.0)
Date Published August 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory , Inc. 2002
PRELIMINARY DATA SHEET
1GB Unbuffered DDR SDRAM DIMM
EBD11ED8ABFB
(128M words
×
72 bits, 2 Banks)
Description
The EBD11ED8ABFB is 128M words
×
72 bits, 2
banks Double Data Rate (DDR) SDRAM unbuffered
module, mounted 18 pieces of 512M bits DDR SDRAM
sealed in TSOP package. Read and write operations
are performed at the cross points of the CK and the
/CK. This high-speed data transfer is realized by the 2
bits prefetch-pipelined architecture. Data strobe (DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. This module provides high
density mounting without utilizing surface mount
technology. Decoupling capacitors are mounted
beside each TSOP on the module board.
Features
184-pin socket type dual in line memory module
(DIMM)
PCB height: 31.75mm
Lead pitch: 1.27mm
2.5V power supply
Data rate: 333Mbps/266Mbps (max.)
2.5 V (SSTL_2 compatible) I/O
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
Data inputs and outputs are synchronized with DQS
4 internal banks for concurrent operation
(Component)
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
referenced to both edges of DQS
Auto precharge option for each burst access
Programmable burst length: 2, 4, 8
Programmable /CAS latency (CL): 2, 2.5
Refresh cycles: (8192 refresh cycles /64ms)
7.8
μ
s maximum average periodic refresh interval
2 variations of refresh
Auto refresh
Self refresh
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| EBD11ED8ADFB-5B | Connector |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EBD11ED8ABFB-6B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Unbuffered DDR SDRAM DIMM EBD11ED8ABFB (128M words 】 72 bits, 2 Banks) |
| EBD11ED8ABFB-7A | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Unbuffered DDR SDRAM DIMM EBD11ED8ABFB (128M words 】 72 bits, 2 Banks) |
| EBD11ED8ABFB-7B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Unbuffered DDR SDRAM DIMM EBD11ED8ABFB (128M words 】 72 bits, 2 Banks) |
| EBD11ED8ADFB | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Unbuffered DDR SDRAM DIMM (128M words x72 bits, 2 Ranks) |
| EBD11ED8ADFB-5 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Unbuffered DDR SDRAM DIMM (128M words x72 bits, 2 Ranks) |
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