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參數(shù)資料
| 型號(hào)： | E80276 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | MITSUBISHI <INTELLIGENT POWER MODULES> FLAT-BASE TYPE INSULATED PACKAGE |
| 中文描述： | 三菱\u003cINTELLIGENT POWER MODULES\u003e平性基地型絕緣包裝 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大小： | 101K |
| 代理商： | E80276 |
Jan. 2000
MITSUBISHI <INTELLIGENT POWER MODULES>
PM15CNJ060
FLAT-BASE TYPE
INSULATED PACKAGE
PRECAUTIONS FOR TESTING
1. Before appling any control supply voltage (V
D
), the input signals should be low level.
After this, each input signal should be set to the specified ON and OFF level.
2. When performing “SC” tests, the turn-off surge voltage spike at the corresponding protection operation should not be
allowed to rise above V
CC(surge)
rating of the device.
(These test should not be done by using a curve tracer or its equivalent.)
10%
90%
trr
Irr
tr
td (on)
tc (on)
tc (off)
td (off)
V
CIN
Ic
Vce
10%
90%
tf
ton= td (on) + tr
toff= td (off) + tf
V
D (all)
Fig. 4 I
CES
Test
U,V,W, (N)
Signal Input
P, (U,V,W)
A
Pulse
V
CE
V
CIN
(15V)
V
D (all)
U,V,W, (N)
Signal Input
P, (U,V,W)
V
CIN
V
CC
I
C
I
C
I
C
OC
SC
V
CIN
t
off (OC)
t
off (OC)
Short Over Current (sc)
Over Current (oc)
Constant Current
Constant Current
U,V,W
N
V
CINN
V
CINP
V
D
V
D
P
Ic
Vcc
V
CINN
0V
0V
V
CINP
t
t
t
dead
t
dead
Fig. 5 OC and SC Test
Fig. 6 OCand SCTestwaveform
Fig. 7 Dead time measurement point example
Fig. 3 Switching time Test circuit and waveform
P, (U,V,W)
P, (U,V,W)
U,V,W, (N)
U,V,W, (N)
VD (all)
VD (all)
V
CIN
(0V)
V
CIN
(15V)
–Ic
Ic
Fig. 1 V
CE(sat)
Test
Fig. 2 V
EC
Test
V
V
a) Lower Arm Switching
P
N
N
U,V,W
Vcc
Vcc
Ic
Ic
V
D
(all)
P
U,V,W
V
D
(all)
V
CIN
V
CIN
Signal input
(Upper Arm)
Signal input
(Lower Arm)
Signal input
(Upper Arm)
Signal input
(Lower Arm)
b) Upper Arm Switching
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