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參數(shù)資料
| 型號(hào)： | E629-EDGE629 |
| 英文描述： | 1 GHz Timing Deskew and Quad Fanout Element |
| 中文描述： | 1 GHz的定時(shí)偏移校正和四扇出元素 |
| 文件頁(yè)數(shù)： | 14/17頁(yè) |
| 文件大小： | 137K |
| 代理商： | E629-EDGE629 |
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6
2000 Semtech Corp.
www .semtech.com
HIGH-PERFORMANCE PRODUCTS – ATE
Edge629
TARGET
Circuit Description
(continued)
Falling Edge Adjustment
The falling edge of a signal may be adjusted to
compensate for any system level pulse width distortion
that may occur. Falling edge adjust (FEA) is accomplished
using an analog delay cell and an on-chip 7 bit DAC (see
Figure 3).
FEA may be bypassed completely by a multiplexer. Also,
FEA affects only the propagation delay of the falling edge.
It has no effect on the propagation delay of a rising edge.
Each channel has its own unique FEA setting and may
be programmed independently from all other channels.
The FEA of any channel will not affect the propagation
delay of any other channel, nor will FEA affect the
propagation delay of a rising edge.
There is a limitation on FEA range vs. pulse width.
Falling Edge Adjust DAC Outputs
DAC_FALL_(0–3) are analog voltage outputs from the on-
board DACs which program the falling edge delay
elements of each channel.
DAC_FALL_(0-3) pins are for test purposes only. Nothing should
be connected to these pins.
Thermal Monitor
The Edge629 features a thermal diode string consisting
of 5 diodes as shown in Figure 4 below.
This string
allows accurate die temperature measurements.
Figure 4. Thermal Diode String
When an external bias current of up to 100
A is injected
through the string, the voltage measured across the
ANODE and CATHODE pins maps directly to the Edge629
junction temperature (see Figure 5).
E
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0
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1s
p
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±
s
p
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9s
p
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s
p
0
8s
p
0
5
2
±
s
p
0
7s
p
0
5
2
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s
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6s
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7 Bit DAC
SFE
T
Figure 3. Falling Edge Adjust Architecture
ANODE
CATHODE
Temperature Coefficient = –7.8 mV/C
Bias Current
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