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參數(shù)資料
| 型號： | E5530H-ZZZ-DOW |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | 128-bit Read-only IDIC for RF Identification |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, UUC2 |
| 封裝： | WAFER-2 |
| 文件頁數(shù)： | 3/5頁 |
| 文件大?。?/td> | 72K |
| 代理商： | E5530H-ZZZ-DOW |
e5530
Rev. A3, 17-Sep-98
3 (5)
PSK
A logical “1” causes (at the end of the bit period) a 180
°
phase shift on the carrier frequency, while a logical “0”
causes no phase shift. The carrier frequency is RF/2.
BIPH
Logical “1” produces a signal which is the same as the bit-
clock and a logical “0” produces a signal of twice the
bitclock period.
Manchester
A logical “1” causes a positive edge in the middle of a bit
period, while a logical “0” causes negative edge.
A combination of BIPH- and FSK-modulation is also
optionally available. The available combinations be-
tween the modulation types and the bitrates are shown in
table “Transmission Options”.
DataClk
Data
PSK
FSK
Biph
Man
1
11
1
00
0
95 10278
Figure 5. Timing diagram for modulation options
Absolute Maximum Ratings
Parameters
Symbol
Value
Unit
Maximum current into Coil1 and Coil2
Icoil
10
mA
Maximum power dissipation (dice)
Ptot
100
mW*
Maximum ambient air temperature with voltage applied
Tamb
–40 to +125
°C
Storage temperature
Tstg
–65 to +150
°C
* Free-air condition. Time of application: 1 s
Stresses above those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device.
Functional operation of the device at these conditions is not imlied.
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