參數(shù)資料
型號: E28F200BX-T120
廠商: INTEL CORP
元件分類: PROM
英文描述: 2-MBIT (128K x 16, 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY
中文描述: 128K X 16 FLASH 12V PROM, 120 ns, PDSO56
封裝: 20 X 14 MM, TSOP-56
文件頁數(shù): 36/48頁
文件大?。?/td> 453K
代理商: E28F200BX-T120
28F200BX-TB 28F002BX-TB
EXTENDED TEMPERATURE OPERATION
AC CHARACTERISTICS FOR WE -CONTROLLED WRITE OPERATIONS(1)
Versions(4)
T28F200BX-80(9)
Unit
T28F002BX-80(9)
Symbol
Parameter
Notes
Min
Max
tAVAV
tWC
Write Cycle Time
80
ns
tPHWL
tPS
RP
High Recovery to
220
ns
WE
Going Low
tELWL
tCS
CE
Setup to WE
Going Low
0
ns
tPHHWH
tPHS
RP
VHH Setup to WE
Going High
6 8
100
ns
tVPWH
tVPS
VPP Setup to WE
Going High
5 8
100
ns
tAVWH
tAS
Address Setup to WE
Going High
3
60
ns
tDVWH
tDS
Data Setup to WE
Going High
4
60
ns
tWLWH
tWP
WE
Pulse Width
60
ns
tWHDX
tDH
Data Hold from WE
High
4
0
ns
tWHAX
tAH
Address Hold from WE
High
3
10
ns
tWHEH
tCH
CE
Hold from WE
High
10
ns
tWHWL
tWPH
WE
Pulse Width High
20
ns
tWHQV1
Duration of WordByte
2 5
7
m
s
Write Operation
tWHQV2
Duration of Erase Operation (Boot)
2 5 6
04
s
tWHQV3
Duration of Erase
2 5
04
s
Operation (Parameter)
tWHQV4
Duration of Erase Operation (Main)
2 5 6
07
s
tQVVL
tVPH
VPP Hold from Valid SRD
5 8
0
ns
tQVPH
tPHH
RP
VHH Hold from Valid SRD
6 8
0
ns
tPHBR
Boot-Block Relock Delay
7 8
100
ns
tIR
Input Rise Time
10
ns
tIF
Input Fall Time
10
ns
NOTES
1 Read timing characteristics during write and erase operations are the same as during read-only operations Refer to AC
characteristics during Read Mode
2 The on-chip WSM completely automates programerase operations programerase algorithms are now controlled inter-
nally which includes verify and margining operations
3 Refer to command definition table for valid AIN
4 Refer to command definition table for valid DIN
5 ProgramErase durations are measured to valid SRD data (successful operation SR7e1)
6 For Boot Block ProgramErase RP
should be held at VHH until operation completes successfully
7 Time tPHBR is required for successful relocking of the Boot Block
8 Sampled but not 100% tested
9 See Standard Test Configuration
41
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