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參數(shù)資料
| 型號(hào)： | E28F016XS-20 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 16-MBIT (1 MBIT x 16, 2 MBIT x 8) SYNCHRONOUS FLASH MEMORY |
| 中文描述： | 2M X 8 FLASH 5V PROM, 30 ns, PDSO56 |
| 封裝： | 14 X 20 MM, TSOP1-56 |
| 文件頁(yè)數(shù)： | 20/37頁(yè) |
| 文件大?。?/td> | 611K |
| 代理商： | E28F016XS-20 |
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BYTE-WIDE SMART 5 FlashFile MEMORY FAMILY
E
20
PRODUCT PREVIEW
SR.7 =
0
1
Start
Write 40H,
Address
Write Byte
Data and Address
Full Status
Check if Desired
Program Complete
FULL STATUS CHECK PROCEDURE
1
0
Read Status Register
Data (See Above)
1
0
Read
Status Register
V Range Error
Bus
Operation
Command
Comments
Standby
Standby
Check SR.3
1 = V Error Detect
SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register
command in cases where multiple locations are written before
full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
Bus
Operation
Command
Comments
Write
Write
Setup
Program
Data = Data to Be Programmed
Addr = Location to Be Programmed
Read
Data = 40H
Addr = Location to Be Programmed
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent byte writes.
SR full status check can be done after each program, or after a
sequence of program operations.
Write FFH after the last program operation to reset device to
read array mode.
Standby
SR.3 =
SR.4 =
Program Error
Program Successful
Program
Status Register Data
Suspend
Program
Yes
No
Suspend
Program Loop
Standby
Check SR.4
1 = Program Error
0
1
Device Protect Error
SR.1 =
Check SR.1
1 = Device Protect Detect
RP# = V , Block Lock-Bit Is Set
Only required for systems
implementing lock-bit configuration
Figure 7. Automated Program Flowchart
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