參數(shù)資料
型號(hào): E28F016XD-85
廠商: INTEL CORP
元件分類: PROM
英文描述: 16-MBIT (1 MBIT x 16) DRAM-INTERFACE FLASH MEMORY
中文描述: 1M X 16 FLASH 5V PROM, 85 ns, PDSO56
封裝: 14 X 20 MM, TSOP-56
文件頁(yè)數(shù): 5/37頁(yè)
文件大?。?/td> 611K
代理商: E28F016XD-85
E
1.0
BYTE-WIDE SMART 5 FlashFile MEMORY FAMILY
5
PRODUCT PREVIEW
INTRODUCTION
This datasheet contains 4-, 8-, and 16-Mbit Smart 5
FlashFile
memory
specifications.
provides a flash memory overview. Sections 2, 3, 4,
and 5 describe the memory organization and
functionality.
Section
specifications
for
commercial
temperature product offerings. The byte-wide Smart
5 FlashFile memory family documentation also
includes application notes and design tools which
are referenced in Appendix B.
Section
1
6
covers
and
electrical
extended
1.1
New Features
The byte-wide Smart 5 FlashFile memory family
maintains
backwards-compatibility
28F008SA. Key enhancements include:
with
Intel’s
SmartVoltage Technology
Enhanced Suspend Capabilities
In-System Block Locking
They share a compatible status register, software
commands, and pinouts. These similarities enable
a clean upgrade from the 28F008SA to byte-wide
Smart 5 FlashFile products. When upgrading, it is
important to note the following differences:
Because of new feature and density options,
the devices have different device identifier
codes. This allows for software optimization.
V
PPLK
has been lowered from 6.5V to 1.5V to
support low V
PP
voltages during block erase,
program, and lock-bit configuration operations.
Designs that switch V
PP
off during read
operations should transition V
PP
to GND.
To take advantage of SmartVoltage tech-
nology, allow V
PP
connection to 5V.
For more details see application note
AP-625,
28F008SC Compatibility with 28F008SA
(order
number 292180)
.
1.2
Product Overview
The byte-wide Smart 5 FlashFile memory family
provides density upgrades with pinout compatibility
for the 4-, 8-, and 16-Mbit densities. The 28F004S5,
28F008S5, and 28F016S5 are high-performance
memories arranged as 512 Kbyte, 1 Mbyte, and
2 Mbyte of 8 bits. This data is grouped in eight,
sixteen, and thirty-two 64-Kbyte blocks which are
individually erasable, lockable, and unlockable in-
system.
Figure
4
illustrates
organization.
the
memory
SmartVoltage technology enables fast factory
programming and low power designs. Specifically
designed for 5V systems, Smart 5 FlashFile
components support read operations at 5V V
CC
and
block erase and program operations at 5V and 12V
V
PP
. The 12V V
PP
option renders the fastest
program performance which will increase your
factory throughput. With the 5V V
PP
option, V
CC
and
V
PP
can be tied together for a simple 5V design. In
addition to the voltage flexibility, the dedicated V
PP
pin
gives
complete
V
PP
V
PPLK
.
data
protection
when
Internal V
PP
detection circuitry
configures the device for optimized block erase and
program operations.
automatically
A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase, program, and lock-bit
configuration operations.
A block erase operation erases one of the device’s
64-Kbyte
blocks
typically
(12V V
PP
), independent of other blocks. Each block
can be independently erased 100,000 times
(1.6 million block erases per device). A block erase
suspend operation allows system software to
suspend block erase to read data from or program
data to any other block.
within
1
second
Data is programmed in byte increments typically
within 6
μ
s (12V V
PP
). A program suspend
operation permits system software to read data or
execute code from any other flash memory array
location.
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