參數(shù)資料
型號(hào)： E28F008SC-120
廠商： INTEL CORP
元件分類(lèi)： PROM
英文描述： BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT
中文描述： 1M X 8 FLASH 3.3V PROM, 120 ns, PDSO40
封裝： 10 X 20 MM, TSOP-40
文件頁(yè)數(shù)： 6/37頁(yè)
文件大?。?/td> 611K
代理商： E28F008SC-120
BYTE-WIDE SMART 5 FlashFile MEMORY FAMILY
6
PRODUCT PREVIEW
To protect programmed data, each block can be
locked. This block locking mechanism uses a
combination of bits, block lock-bits and a master
lock-bit, to lock and unlock individual blocks. The
block lock-bits gate block erase and program
operations, while the master lock-bit gates block
lock-bit configuration operations. Lock-bit config-
uration operations (Set Block Lock-Bit, Set Master
Lock-Bit, and Clear Block Lock-Bits commands) set
and clear lock-bits.
The status register and RY/BY# output indicate
whether or not the device is busy executing or
ready for a new command. Polling the status
register, system software retrieves WSM feedback.
The RY/BY# output gives an additional indicator of
WSM activity by providing a hardware status signal.
Like the status register, RY/BY#-low indicates that
the WSM is performing a block erase, program, or
lock-bit configuration. RY/BY#-high indicates that
the WSM is ready for a new command, block erase
is suspended (and program is inactive), program is
suspended, or the device is in deep power-down
mode.
The Automatic Power Savings (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical I
CCR
current is 1 mA.
When CE# and RP# pins are at V
CC
, the
component enters a CMOS standby mode. Driving
RP# to GND enables a deep power-down mode
which significantly reduces power consumption,
provides write protection, resets the device, and
clears the status register. A reset time (t
PHQV
) is
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (t
PHEL
)
from RP#-high until writes to the CUI are
recognized.
1.3
Pinout and Pin Description
The family of devices is available in 40-lead TSOP
(Thin Small Outline Package, 1.2 mm thick) and
44-lead PSOP (Plastic Small Outline Package).
Pinouts are shown in Figures 2 and 3.
4-Mbit: A - A ,
8-Mbit: A - A ,
16-Mbit: A - A
Input
Buffer
Output
Buffer
Identifier
Register
Status
Register
Command
Register
I/O Logic
Data
Comparator
Input
Buffer
Address
Latch
Address
Counter
Y
Decoder
X
Decoder
Y Gating
4-Mbit: Eight
8-Mbit: Sixteen
16-Mbit: Thirty-Two
64-Kbyte Blocks
Write State
Machine
Program/Erase
Voltage Switch
CE#
WE#
OE#
RP#
RY/BY#
V
V
GND
DQ - DQ
PP
V
CC
7
Figure 1. Block Diagram
相關(guān)PDF資料
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