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| 型號(hào)： | DVI |
| 英文描述： | DVI Protection (92k) |
| 中文描述： | DVI接口保護(hù)（92k） |
| 文件頁(yè)數(shù)： | 1/2頁(yè) |
| 文件大?。?/td> | 92K |
| 代理商： | DVI |
PROTECTION PRODUCTS
1
www.semtech.com
SI01-15
Surging
Ideas
TVS Diode Application Note
Revision 02/04/2002
DVI Protection
The industry’s demand for high-resolution flat panels
requires more complex digital and analog solutions in a
dense area. The small geometry’s of the digital-visual
interface (DVI) graphic chip makes it more susceptible
to electrostatic discharges (ESD) and cable discharge
events (CDE). The industry ESD standard is IEC61000-
4-2. It requires the system to withstand 8kV contact
and 15kV air ESD.
Transient protection of a DVI port can be challenging.
Digital-visual interfaces can often transmit and receive
at a rate equal to or above 1Gbps. The high-speed
data transmission requires the protection device to
have low capacitance to maintain signal integrity and
low clamping voltage to reduce stress on the protected
IC. The SRV05-4 TVS array is specifically designed for
this application.
The SRV05-4 has a low capacitance of 3pF from any
I/O pin (pin 1,3,4 or 6) to ground (pin 2) or 1.5pF from
any I/O pin to I/O pin. The insertion loss characteristic
of the SRV05-4 is shown in Figure 2. The graph shows
that the device has a low insertion loss of 0.4dB at
1GHz (I/O to ground). The SRV05-4 is also designed to
withstand the energy of a 15kV air and 8kV contact
ESD event. Figure 3 shows that the SRV05-4 clamps
an 8kV contact ESD surge to less than 20V. The
SRV05-4 will also protect the DVI graphic chip against
CDE.
Figure 4 shows how to design the SRV05-4 into the
DVI circuit on the flat panel display and in a PC graphic
card. The SRV05-4 is configured to provide common
mode and differential mode protection. The internal
TVS of the SRV05-4 acts as a 5 volt reference. The
power pin of the DVI circuit does not come out through
the connector and is not subjected to external ESD
pulse; therefore, pin 5 should be left unconnected.
Connecting pin 5 to Vcc of the DVI circuit may result in
damage to the chip from ESD current.
Figure 1 - SRV05-4 Schematic
3 dB/
CH1
S21
LOG
REF 0 dB
START
.030 000 MHz
Figure 2 - SRV05-4 Insertion Loss
STOP 3 000.000 000 MHz
Figure 3 - SRV05-4 8kV contact ESD Response
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