參數(shù)資料
型號(hào)： DT72V3674L15PF
廠商： Integrated Device Technology, Inc.
英文描述： 3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2 4,096 x 36 x 2 8,192 x 36 x 2
中文描述： 3.3伏的CMOS SyncBiFIFOTM與巴士，匹配2048 × 36 × 2 4096 × 36 × 2 8192 × 36 × 2
文件頁(yè)數(shù)： 1/37頁(yè)
文件大?。?/td> 416K
代理商： DT72V3674L15PF
1
NOVEMBER 2003
IDT72V3654
IDT72V3664
IDT72V3674
3.3 VOLT CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
2,048 x 36 x 2
4,096 x 36 x 2
8,192 x 36 x 2
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4664/4
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Memory storage capacity:
IDT72V3654
IDT72V3664
IDT72V3674
Clock frequencies up to 100 MHz (6.5ns access time)
Two independent clocked FIFOs buffering data in opposite
directions
Select IDT Standard timing (using
EFA
,
EFB
,
FFA
, and
FFB
flags
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRB flag functions)
Programmable Almost-Empty and Almost-Full flags; each has five
default offsets (8, 16, 64, 256 and 1,024 )
Serial or parallel programming of partial flags
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
–
–
–
2,048 x 36 x 2
4,096 x 36 x 2
8,192 x 36 x 2
Big- or Little-Endian format for word and byte bus sizes
Retransmit Capability
Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA and CLKB may be asynchronous or coincident
(simultaneous reading and writing of data on a single clock edge
is permitted)
Auto power down minimizes power dissipation
Available in space saving 128-pin Thin Quad Flatpack (TQFP)
Pin and functionally compatible version of the 5V operating
IDT723654/723664/723674
Pin compatible to the lower density parts, IDT72V3624/72V3634/
72V3644
Industrial temperature range (–40
°
C to +85
°
C) is available
Mail 1
Register
Programmable Flag
Offset Registers
I
R
2,048 x 36
4,096 x 36
8,192 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
I
R
O
R
2,048 x 36
4,096 x 36
8,192 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
CLKA
CSA
W/
R
A
ENA
MBA
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
MRS1
Mail 2
Register
MBF2
CLKB
CSB
W
/RB
ENB
MBB
BE
BM
SIZE
Port-B
Control
Logic
FIFO2,
Mail2
Reset
Logic
MRS2
MBF1
FIFO1
FIFO2
13
EFB
/ORB
AEB
36
36
FFB
/IRB
AFB
B
0
-B
35
FFA
/IRA
AFA
FS2
FS0/SD
FS1/
SEN
A
0
-A
35
EFA
/ORA
AEA
4664 drw01
36
36
O
M
O
R
PRS2
PRS1
Timing
Mode
FWFT
36
36
36
36
I
M
FIFO1 and
FIFO2
Retransmit
Logic
RT1
RT2
RTM
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