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參數(shù)資料
| 型號： | DT70V27S |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM |
| 中文描述： | 高速3.3 32K的× 16 DUAL-PORT靜態(tài)RAM |
| 文件頁數(shù)： | 1/22頁 |
| 文件大?。?/td> | 192K |
| 代理商： | DT70V27S |
2000 Integrated Device Technology, Inc.
6.01
1
DSC 3603/7
N
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
N
High-speed access
– Industrial: 35ns (max.)
– Commercial: 15/20/25/35/55ns (max.)
N
Low-power operation
– IDT70V27S
Active: 500mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V27L
Active: 500mW (typ.)
Standby: 660
μ
W (typ.)
N
Separate upper-byte and lower-byte control for bus
matching capability
N
Dual chip enables allow for depth expansion without
external logic
IDT70V27S/L
N
IDT70V27 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
N
M/
S
= V
IH
for
BUSY
output flag on Master,
M/
S
= V
IL
for
BUSY
input on Slave
N
Busy and Interrupt Flags
N
On-chip port arbitration logic
N
Full on-chip hardware support of semaphore signaling
between ports
N
Fully asynchronous operation from either port
N
LVTTL-compatible, single 3.3V (±0.3V) power supply
N
Available in 100-pin Thin Quad Flatpack (TQFP), 108-pin
Ceramic Pin Grid Array (PGA), and 144-pin Fine Pitch BGA
(fpBGA)
N
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
I/O
Control
Address
Decoder
32Kx16
MEMORY
ARRAY
70V27
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
0L
CE
1L
OE
L
R/
W
L
A
14L
A
0L
A
14L
A
0L
SEM
L
INT
L
(2)
BUSY
L
(1,2)
LB
L
CE
0L
CE
1L
OE
L
UB
L
I/O
Control
Address
Decoder
CE
0R
CE
1R
OE
R
R/
W
R
A
14R
A
0R
A
14R
A
0R
SEM
R
INT
R
(2)
BUSY
R
(1,2)
LB
R
R/
W
R
UB
R
OE
R
M/
S
(2)
CE
0R
CE
1R
3603 drw 01
I/O
0-7L
I/O
8-15L
I/O
0-7R
I/O
8-15R
R/
W
L
NOTES:
1)
BUSY
is an input as a Slave (M/
S
=V
IL
) and an output as a Master (M/
S
=V
IH
).
2)
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
HIGH-SPEED 3.3V
32K x 16 DUAL-PORT
STATIC RAM
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