參數(shù)資料
型號(hào): DT28F160S3-120
廠商: INTEL CORP
元件分類: DRAM
英文描述: 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor
中文描述: 1M X 16 FLASH 2.7V PROM, 120 ns, PDSO56
封裝: 16 X 23.70 MM, SSOP-56
文件頁數(shù): 44/52頁
文件大小: 1262K
代理商: DT28F160S3-120
28F160S3, 28F320S3
E
44
ADVANCE INFORMATION
6.2.4
AC CHARACTERISTICS - READ-ONLY OPERATIONS
Table 20.
AC Read Characteristics
(1,5)
, T
A
=
–40
o
C to +85
o
C
Versions
(4)
3.3V ± 0.3V V
CC
-100/-110
-130/-140
(All units in ns unless otherwise noted)
2.7V - 3.6V V
CC
-120/-130
-150/-160
#
Sym
Parameter
Notes Min
Max
Min
Max
Min
Max
Min
Max
R1 t
AVAV
Read/Write Cycle Time
16 Mbit
1
100
120
130
150
32 Mbit
1
110
130
140
160
R2 t
AVQV
Address to Output Delay
16 Mbit
1
100
120
130
150
32 Mbit
1
110
130
140
160
R3 t
ELQV
CE
X
# to Output Delay
16 Mbit
2
100
120
130
150
32 Mbit
2
110
130
140
160
R4 t
GLQV
OE# to Output Delay
2
45
50
50
55
R5 t
PHQV
RP# High to Output Delay
600
600
600
600
R6 t
ELQX
CE
X
# to Output in Low Z
3
0
0
0
0
R7 t
GLQX
OE# to Output in Low Z
3
0
0
0
0
R8 t
EHQZ
CE
X
# High to Output in High Z
3
50
50
55
55
R9 t
GHQZ
OE# High to Output in High Z
3
20
20
25
25
R10 t
OH
Output Hold from Address, CE
X
#, or
OE# Change, Whichever Occurs First
3
0
0
0
0
R11 t
ELFL
t
ELFH
CE
X
# Low to BYTE# High or Low
3
5
5
5
5
R12 t
FLQV
t
FHQV
BYTE# to Output Delay
16 Mbit
3
100
120
130
150
32 Mbit
3
110
130
140
160
R13 t
FLQZ
BYTE# to Output in High Z
3
30
30
40
40
NOTES:
1.
2.
3.
4.
5.
See AC Input/Output Reference Waveform for maximum allowable input slew rate.
OE# may be delayed up to t
ELQV
-t
GLQV
after the falling edge of CE
X
# without impact on t
ELQV
.
Sampled, not 100% tested.
See Ordering Information for device speeds (valid operational combinations).
See Figures 14 through 16 for testing characteristics.
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