參數(shù)資料
型號: DSPIC33FJ12MC201-E/SO
廠商: Microchip Technology
文件頁數(shù): 104/155頁
文件大小: 0K
描述: IC DSPIC MCU/DSP 12K 20SOIC
產品培訓模塊: Asynchronous Stimulus
標準包裝: 38
系列: dsPIC™ 33F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: I²C,IrDA,SPI,UART/USART
外圍設備: 高級欠壓探測/復位,電機控制 PWM,QEI,POR,PWM,WDT
輸入/輸出數(shù): 15
程序存儲器容量: 12KB(12K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據轉換器: A/D 4x10b
振蕩器型: 內部
工作溫度: -40°C ~ 125°C
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
包裝: 管件
配用: DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
52
A/T89C51AC2
4127H–8051–02/08
Figure 29. UART Timing in Mode 1
Figure 30. UART Timing in Modes 2 and 3
Automatic Address
Recognition
The automatic address recognition feature is enabled when the multiprocessor commu-
nication feature is enabled (SM2 bit in SCON register is set).
Implemented in the hardware, automatic address recognition enhances the multiproces-
sor communication feature by allowing the serial port to examine the address of each
incoming command frame. Only when the serial port recognizes its own address will the
receiver set the RI bit in the SCON register to generate an interrupt. This ensures that
the CPU is not interrupted by command frames addressed to other devices.
If necessary, you can enable the automatic address recognition feature in mode 1. In
this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when
the received command frame address matches the device’s address and is terminated
by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and
a broadcast address.
Note:
The multiprocessor communication and automatic address recognition features cannot
be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).
Data byte
RI
SMOD0=X
Stop
bit
Start
bit
RXD
D7
D6
D5
D4
D3
D2
D1
D0
FE
SMOD0=1
RI
SMOD0=0
Data byte
Ninth
bit
Stop
bit
Start
bit
RXD
D8
D7
D6
D5
D4
D3
D2
D1
D0
RI
SMOD0=1
FE
SMOD0=1
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