參數(shù)資料
型號： DSPIC30F4013-30I/P
廠商： Microchip Technology
文件頁數(shù)： 109/153頁
文件大?。?/td> 0K
描述： IC DSPIC MCU/DSP 48K 40DIP
產(chǎn)品培訓(xùn)模塊： Serial Communications using dsPIC30F CAN
Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標(biāo)準(zhǔn)包裝： 10
系列： dsPIC™ 30F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 30 MIP
連通性： CAN，I²C，SPI，UART/USART
外圍設(shè)備： AC'97，欠壓檢測/復(fù)位，I²S，POR，PWM，WDT
輸入/輸出數(shù)： 30
程序存儲器容量： 48KB（16K x 24）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 13x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
產(chǎn)品目錄頁面： 651 (CN2011-ZH PDF)
配用： AC30F003-ND - MODULE SOCKET DSPIC30F 40DIP
DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
ACICE0206-ND - ADAPTER MPLABICE 40P 600 MIL
其它名稱： DSPIC30F4013-30IP
2010 Microchip Technology Inc.
DS70138G-page 59
dsPIC30F3014/4013
8.0
INTERRUPTS
The dsPIC30F sensor and general purpose families
have up to 41 interrupt sources and 4 processor excep-
tions (traps) which must be arbitrated based on a
priority scheme.
The CPU is responsible for reading the Interrupt Vector
Table (IVT) and transferring the address contained in
the interrupt vector to the program counter. The inter-
rupt vector is transferred from the program data bus
into the program counter via a 24-bit wide multiplexer
on the input of the program counter.
The Interrupt Vector Table (IVT) and Alternate Interrupt
Vector Table (AIVT) are placed near the beginning of
program memory (0x000004). The IVT and AIVT are
shown in Figure 8-1.
The
interrupt
controller
is
responsible
for
pre-
processing the interrupts and processor exceptions
prior to them being presented to the processor core.
The peripheral interrupts and traps are enabled,
prioritized and controlled using centralized Special
Function Registers:
IFS0<15:0>, IFS1<15:0>, IFS2<15:0>
All interrupt request flags are maintained in these
three registers. The flags are set by their respec-
tive peripherals or external signals and they are
cleared via software.
IEC0<15:0>, IEC1<15:0>, IEC2<15:0>
All interrupt enable control bits are maintained in
these three registers. These control bits are used
to individually enable interrupts from the
peripherals or external signals.
IPC0<15:0>... IPC10<7:0>
The user-assignable priority level associated with
each of these 41 interrupts is held centrally in
these eleven registers.
IPL<3:0>
The current CPU priority level is explicitly stored
in the IPL bits. IPL<3> is present in the CORCON
register, whereas IPL<2:0> are present in the
STATUS register (SR) in the processor core.
INTCON1<15:0>, INTCON2<15:0>
Global interrupt control functions are derived from
these two registers. INTCON1 contains the con-
trol and status flags for the processor exceptions.
The INTCON2 register controls the external
interrupt request signal behavior and the use of
the alternate vector table.
All interrupt sources can be user-assigned to one of
7 priority levels, 1 through 7, via the IPCx registers.
Each interrupt source is associated with an interrupt
vector, as shown in Table 8-1. Levels 7 and 1 represent
the
highest
and
lowest
maskable
priorities,
respectively.
If the NSTDIS bit (INTCON1<15>) is set, nesting of
interrupts is prevented. Thus, if an interrupt is currently
being serviced, processing of a new interrupt is pre-
vented even if the new interrupt is of higher priority than
the one currently being serviced.
Certain interrupts have specialized control bits for
features like edge or level triggered interrupts, inter-
rupt-on-change, etc. Control of these features remains
within the peripheral module which generates the
interrupt.
The DISI instruction can be used to disable the
processing of interrupts of priorities 6 and lower for a
certain number of instructions, during which the DISI bit
(INTCON2<14>) remains set.
When an interrupt is serviced, the PC is loaded with the
address stored in the vector location in program
memory that corresponds to the interrupt. There are
63 different vectors within the IVT (refer to Table 8-1)
These vectors are contained in locations 0x000004
through 0x0000FE of program memory (refer to
Table 8-1). These locations contain 24-bit addresses.
In order to preserve robustness, an address error trap
takes place should the PC attempt to fetch any of these
words during normal execution. This prevents execu-
tion of random data as a result of accidentally
decrementing a PC into vector space, accidentally
mapping a data space address into vector space or the
PC rolling over to 0x000000 after reaching the end of
implemented program memory space. Execution of a
GOTO
instruction to this vector space also generates an
address error trap.
Note:
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals,
register
descriptions
and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC Pro-
grammer’s
Reference
Manual”
(DS70157).
Note:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit. User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
Note:
Assigning a priority level of ‘0’ to an inter-
rupt source is equivalent to disabling that
interrupt.
Note:
The IPL bits become read-only whenever
the NSTDIS bit has been set to ‘1’.
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