參數(shù)資料
型號(hào): DSPIC30F3012-20I/ML
廠商: Microchip Technology
文件頁數(shù): 61/161頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 24K 44QFN
產(chǎn)品培訓(xùn)模塊: Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標(biāo)準(zhǔn)包裝: 45
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 20 MIPS
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 12
程序存儲(chǔ)器容量: 24KB(8K x 24)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VQFN 裸露焊盤
包裝: 管件
配用: XLT44QFN5-ND - SOCKET TRANS ICE 18DIP TO 44QFN
AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
其它名稱: DSPIC30F301220IML
2011 Microchip Technology Inc.
DS39932D-page 183
PIC18F46J11 FAMILY
11.2.5
ADDRESSABLE PARALLEL SLAVE
PORT MODE
In the Addressable Parallel Slave Port mode
(PMMODEH<1:0> = 01), the module is configured with
two extra inputs, PMA<1:0>, which are the address
lines 1 and 0. This makes the 4-byte buffer space
directly addressable as fixed pairs of read and write
buffers. As with Legacy Buffered mode, data is output
from PMDOUT1L, PMDOUT1H, PMDOUT2L and
PMDOUT2H, and is read in on PMDIN1L, PMDIN1H,
PMDIN2L and PMDIN2H. Table 11-1 provides the
buffer addressing for the incoming address to the input
and output registers.
TABLE 11-1:
SLAVE MODE BUFFER
ADDRESSING
FIGURE 11-6:
PARALLEL MASTER/SLAVE CONNECTION ADDRESSED BUFFER EXAMPLE
11.2.5.1
READ FROM SLAVE PORT
When chip select is active and a read strobe occurs
(PMCS = 1 and PMRD = 1), the data from one of the
four output bytes is presented onto PMD<7:0>. Which
byte is read depends on the 2-bit address placed on
ADDR<1:0>. Table 11-1 provides the corresponding
output registers and their associated address. When an
output buffer is read, the corresponding OBxE bit is set.
The OBxE flag bit is set when all the buffers are empty.
If any buffer is already empty, OBxE = 1, the next read
to that buffer will generate an OBUF event.
FIGURE 11-7:
PARALLEL SLAVE PORT READ WAVEFORMS
PMA<1:0>
Output
Register
(Buffer)
Input Register
(Buffer)
00
PMDOUT1L (0)
PMDIN1L (0)
01
PMDOUT1H (1)
PMDIN1H (1)
10
PMDOUT2L (2)
PMDIN2L (2)
11
PMDOUT2H((3)
PMDIN2H (3)
PMD<7:0>
PMRD
PMWR
Master
PMCS
PMA<1:0>
Address Bus
Data Bus
Control Lines
PMRD
PMWR
PIC18F Slave
PMCS
PMDOUT1L (0)
PMDOUT1H (1)
PMDOUT2L (2)
PMDOUT2H (3)
PMDIN1L (0)
PMDIN1H (1)
PMDIN2L (2)
PMDIN2H (3)
PMD<7:0>
Write
Address
Decode
Read
Address
Decode
PMA<1:0>
|
Q4
|
Q1
|
Q2
|
Q3
|
Q4
PMCS
PMWR
PMRD
PMD<7:0>
PMA<1:0>
OBE
PMPIF
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