參數(shù)資料
      型號(hào): DSPIC30F2012T-20I/ML
      廠商: Microchip Technology
      文件頁數(shù): 28/66頁
      文件大?。?/td> 0K
      描述: IC DSPIC MCU/DSP 12K 28QFN
      產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
      標(biāo)準(zhǔn)包裝: 1,600
      系列: dsPIC™ 30F
      核心處理器: dsPIC
      芯體尺寸: 16-位
      速度: 20 MIPS
      連通性: I²C,SPI,UART/USART
      外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
      輸入/輸出數(shù): 20
      程序存儲(chǔ)器容量: 12KB(4K x 24)
      程序存儲(chǔ)器類型: 閃存
      RAM 容量: 1K x 8
      電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
      數(shù)據(jù)轉(zhuǎn)換器: A/D 10x12b
      振蕩器型: 內(nèi)部
      工作溫度: -40°C ~ 85°C
      封裝/外殼: 28-VQFN 裸露焊盤
      包裝: 帶卷 (TR)
      dsPIC30F Flash Programming Specification
      DS70102K-page 34
      2010 Microchip Technology Inc.
      11.0 ICSP MODE
      11.1
      ICSP Mode
      ICSP mode is a special programming protocol that
      allows you to read and write to the dsPIC30F program-
      ming executive. The ICSP mode is the second (and
      slower) method used to program the device. This mode
      also has the ability to read the contents of executive
      memory to determine whether the programming exec-
      utive is present. This capability is accomplished by
      applying control codes and instructions serially to the
      device using pins PGC and PGD.
      In ICSP mode, the system clock is taken from the PGC
      pin, regardless of the device’s oscillator Configuration
      bits. All instructions are first shifted serially into an
      internal buffer, then loaded into the Instruction register
      and executed. No program fetching occurs from
      internal memory. Instructions are fed in 24 bits at a
      time. PGD is used to shift data in and PGC is used as
      both the serial shift clock and the CPU execution clock.
      Data is transmitted on the rising edge and latched on
      the falling edge of PGC. For all data transmissions, the
      Least Significant bit (LSb) is transmitted first.
      11.2
      ICSP Operation
      Upon entry into ICSP mode, the CPU is idle. Execution
      of the CPU is governed by an internal state machine. A
      4-bit control code is clocked in using PGC and PGD,
      and this control code is used to command the CPU
      (see Table 11-1).
      The SIX control code is used to send instructions to the
      CPU for execution, while the REGOUT control code is
      used to read data out of the device via the VISI register.
      The operation details of ICSP mode are provided in
      TABLE 11-1:
      CPU CONTROL CODES IN
      ICSP MODE
      4-bit
      Control
      Code
      Mnemonic
      Description
      0000b
      SIX
      Shift in 24-bit instruction
      and execute.
      0001b
      REGOUT
      Shift out the VISI
      register.
      0010b-1111b N/A
      Reserved.
      11.2.1
      SIX SERIAL INSTRUCTION
      EXECUTION
      The SIX control code allows execution of dsPIC30F
      assembly instructions. When the SIX code is received,
      the CPU is suspended for 24 clock cycles as the
      instruction is then clocked into the internal buffer. Once
      the instruction is shifted in, the state machine allows it
      to be executed over the next four clock cycles. While
      the received instruction is executed, the state machine
      simultaneously shifts in the next 4-bit command (see
      Note 1: During ICSP operation, the operating
      frequency of PGC must not exceed
      5 MHz.
      2: Because ICSP is slower, it is recom-
      mended that only Enhanced ICSP (E-
      ICSP) mode be used for device program-
      ming, as described in Section 5.1
      Note 1: Coming out of the ICSP entry sequence,
      the first 4-bit control code is always
      forced to SIX and a forced NOP instruc-
      tion is executed by the CPU. Five addi-
      tional PGC clocks are needed on start-
      up, thereby resulting in a 9-bit SIX com-
      mand instead of the normal 4-bit SIX
      command. After the forced SIX is clocked
      in, ICSP operation resumes as normal
      (the next 24 clock cycles load the first
      instruction word to the CPU). See
      Figure 11-1 for details.
      2: TBLRDH, TBLRDL, TBLWTH and TBLWTL
      instructions must be followed by a NOP
      instruction.
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