參數(shù)資料
型號: DSPIC30F2010T-20I/MM
廠商: Microchip Technology
文件頁數(shù): 14/49頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 12K 28QFN
產品培訓模塊: Asynchronous Stimulus
標準包裝: 1,600
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 20 MIPS
連通性: I²C,SPI,UART/USART
外圍設備: 高級欠壓探測/復位,電機控制 PWM,QEI,POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲器容量: 12KB(4K x 24)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 6x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-VQFN 裸露焊盤
包裝: 帶卷 (TR)
2011 Microchip Technology Inc.
DS70118J-page 21
dsPIC30F2010
3.1.1
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
This architecture fetches 24-bit wide program memory.
Consequently, instructions are always aligned. How-
ever, as the architecture is modified Harvard, data can
also be present in program space.
There are two methods by which program space can
be accessed: via special table instructions, or through
the remapping of a 16K word program space page into
the upper half of data space (see Section 3.1.2 “Data
Space Visibility”). The TBLRDL and TBLWTL instruc-
tions offer a direct method of reading or writing the lsw
of any address within program space, without going
through data space. The TBLRDH and TBLWTH instruc-
tions are the only method whereby the upper 8 bits of a
program space word can be accessed as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
word wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the least significant
data word, and TBLRDH and TBLWTH access the space
which contains the Most Significant data Byte.
Figure 3-2 shows how the EA is created for table oper-
ations and data space accesses (PSV = 1). Here,
P<23:0> refers to a program space word, whereas
D<15:0> refers to a data space word.
A set of Table Instructions are provided to move byte or
word-sized data to and from program space.
1.
TBLRDL:
Table Read Low
Word: Read the least significant word of the
program address;
P<15:0> maps to D<15:0>.
Byte: Read one of the LSBs of the program
address;
P<7:0> maps to the destination byte when byte
select = 0;
P<15:8> maps to the destination byte when byte
select = 1.
2.
TBLWTL:
Table Write Low (refer to Section 6.0
“Flash Program Memory” for details on Flash
Programming).
3.
TBLRDH:
Table Read High
Word: Read the most significant word of the
program address;
P<23:16> maps to D<7:0>; D<15:8> always
be = 0.
Byte: Read one of the MSBs of the program
address;
P<23:16> maps to the destination byte when
byte select = 0;
The destination byte will always be = 0 when
byte select = 1.
4.
TBLWTH:
Table Write High (refer to Section 6.0
“Flash Program Memory” for details on Flash
Programming).
FIGURE 3-3:
PROGRAM DATA TABLE ACCESS (LEAST SIGNIFICANT WORD)
0
8
16
PC Address
0x000000
0x000002
0x000004
0x000006
23
00000000
Program Memory
‘Phantom’ Byte
(Read as ‘0’)
TBLRDL.W
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
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