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參數(shù)資料
型號(hào): DSPB56371AF180
廠商: Freescale Semiconductor
文件頁數(shù): 8/68頁
文件大?。?/td> 0K
描述: IC DSP 24BIT 180MHZ 80-LQFP
標(biāo)準(zhǔn)包裝: 90
系列: DSP56K/Symphony
類型: 音頻處理器
接口: 主機(jī)接口,I²C,SAI,SPI
時(shí)鐘速率: 180MHz
非易失內(nèi)存: ROM(384 kB)
芯片上RAM: 264kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.25V
工作溫度: -40°C ~ 115°C
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-LQFP(14x14)
包裝: 托盤
DSP56371 Data Sheet, Rev. 4.1
Signal/Connection Descriptions
Freescale Semiconductor
16
3.7
Serial Host Interface
The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode.
MODB/IRQB
Input
Mode Select B/External Interrupt Request B—MODB/IRQB is an active-low
Schmitt-trigger input, internally synchronized to the DSP clock. MODB/IRQB
selects the initial chip operating mode during hardware reset and becomes a
level-sensitive or negative-edge-triggered, maskable interrupt request input
during normal instruction processing. MODA, MODB, MODC and MODD select
one of 16 initial chip operating modes, latched into OMR when the RESET signal
is deasserted.
Internal Pull up resistor.
This input is 5 V tolerant.
MODC/IRQC
Input
Mode Select C/External Interrupt Request C—MODC/IRQC is an active-low
Schmitt-trigger input, internally synchronized to the DSP clock. MODC/IRQC
selects the initial chip operating mode during hardware reset and becomes a
level-sensitive or negative-edge-triggered, maskable interrupt request input
during normal instruction processing. MODA, MODB, MODC and MODD select
one of 16 initial chip operating modes, latched into OMR when the RESET signal
is deasserted.
Internal Pull up resistor.
This input is 5 V tolerant.
MODD/IRQD
Input
Mode Select D/External Interrupt Request D—MODD/IRQD is an active-low
Schmitt-trigger input, internally synchronized to the DSP clock. MODD/IRQD
selects the initial chip operating mode during hardware reset and becomes a
level-sensitive or negative-edge-triggered, maskable interrupt request input
during normal instruction processing. MODA, MODB, MODC and MODD select
one of 16 initial chip operating modes, latched into OMR when the RESET signal
is deasserted.
Internal Pull up resistor.
This input is 5 V tolerant.
RESET
Input
Reset—RESET is an active-low, Schmitt-trigger input. When asserted, the chip
is placed in the Reset state and the internal phase generator is reset. The
Schmitt-trigger input allows a slowly rising input (such as a capacitor charging)
to reset the chip reliably. When the RESET signal is deasserted, the initial chip
operating mode is latched from the MODA, MODB, MODC and MODD inputs.
The RESET signal must be asserted during power up. A stable EXTAL signal
must be supplied while RESET is being asserted.
Internal Pull up resistor.
This input is 5 V tolerant.
Table 6. Interrupt and Mode Control (continued)
Signal Name
Type
State
During
Reset
Signal Description
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