參數(shù)資料
型號： DSP56F807VF80E
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號控制器
文件頁數(shù)： 24/60頁
文件大?。?/td> 522K
代理商： DSP56F807VF80E
56F807 Technical Data Technical Data, Rev. 15
24
Freescale Semiconductor
Output Low Voltage (at IOL)
V
OL
—
—
0.4
V
Output source current
I
OH
4
—
—
mA
Output source current
I
OL
4
—
—
mA
PWM pin output source current
3
I
OHP
10
—
—
mA
PWM pin output sink current
4
I
OLP
16
—
—
mA
Input capacitance
C
IN
—
8
—
pF
Output capacitance
C
OUT
—
12
—
pF
V
DD
supply current
I
DDT5
Run
6
—
195
220
mA
Wait
7
—
170
200
mA
Stop
—
115
145
mA
Low Voltage Interrupt, external power supply
8
V
EIO
2.4
2.7
3.0
V
Low Voltage Interrupt, internal power supply
9
V
EIC
2.0
2.2
2.4
V
Power on Reset
10
V
POR
—
1.7
2.0
V
1.
TDI, and MSCAN_RX
Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, TCS, ISA0-2, FAULTA0-3, ISB0-2, FAULTB0-3, TCK, TRST, TMS,
2.
Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.
3.
PWM pin output source current measured with 50% duty cycle.
4.
PWM pin output sink current measured with 50% duty cycle.
5.
I
DDT
= I
DD
+ I
DDA
(Total supply current for V
DD
+ V
DDA
)
Run (operating) I
DD
measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as inputs;
measured with all modules enabled.
6.
7.
than 50pF on all outputs. C
L
= 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait I
DD
; measured
with PLL enabled.
Wait I
DD
measured using external square wave clock source (f
osc
= 8MHz) into XTAL; all inputs 0.2V from rail; no DC loads; less
8.
separate traces. If V
DDA
drops below V
EIO
, an interrupt is generated. Functionality of the device is guaranteed under transient condi-
tions when V
DDA
>V
EIO
(between the minimum specified V
DD
and the point when the V
EIO
interrupt is generated).
9.
This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is regulator
drops below V
EIC
, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not be generated unless
the external power supply drops below the minimum specified value (3.0V).
10. Power
–
on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is ramping up,
this signal remains active as long as the internal 2.5V is below 1.5V typical, no matter how long the ramp-up rate is. The internally
regulated voltage is typically 100mV less than V
DD
during ramp-up until 2.5V is reached, at which time it self-regulates.
This low voltage interrupt monitors the V
DDA
external power supply. V
DDA
is generally connected to the same potential as V
DD
via
Table 3-4 DC Electrical Characteristics (Continued)
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40
°
to +85
°
C, C
L
≤
50pF, f
op
= 80MHz
Characteristic
Symbol
Min
Typ
Max
Unit
相關PDF資料
PDF描述
DSP56F807 16-bit Hybrid Controller(16位混合控制器)
DSP56F826BU80 16-bit Digital Signal Controllers
DSP56F826BU80E 16-bit Digital Signal Controllers
DSP56F826E 16-bit Digital Signal Controllers
DSP56F826 16-bit Hybrid Controller(16位混合控制器)
相關代理商/技術參數(shù)
參數(shù)描述
DSP56F807VF80E 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC
DSP56F807VF80J 制造商:Freescale Semiconductor 功能描述:DSP 16BIT - Trays
DSP56F826 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
DSP56F826-827UM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor Users Manual
DSP56F826-827UM/D 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:56F827 16-bit Hybrid Controller
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*