參數(shù)資料
型號： DSP56858FV120
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號控制器
文件頁數(shù)： 33/64頁
文件大?。?/td> 956K
代理商： DSP56858FV120
Reset, Stop, Wait, Mode Select, and Interrupt Timing
56858 Technical Data, Rev. 6
Freescale Semiconductor
33
4.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 4-8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1, 2
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
=
3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
≤
50pF, f
op
= 120MHz
1.
In the formulas, T = clock cycle. For f
op
= 120MHz operation and f
ipb
= 60MHz, T = 8.33ns.
Parameters listed are guaranteed by design.
2.
Characteristic
Symbol
Min
Max
Unit
See Figure
RESET Assertion to Address, Data and Control
Signals High Impedance
t
RAZ
—
11
ns
Figure 4-11
Minimum RESET Assertion Duration
3
3.
t
xtal
, t
extal
or t
osc
.
4.
The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not
the minimum required so that the IRQA interrupt is accepted.
At reset, the PLL is disabled and bypassed. The part is then put into Run mode and t
clk
assumes the period of the source clock,
t
RA
30
—
ns
Figure 4-11
RESET Deassertion to First External Address Output
t
RDA
—
120T
ns
Figure 4-11
Edge-sensitive Interrupt Request Width
t
IRW
1T + 3
—
ns
Figure 4-12
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine
t
IDM
18T
—
ns
Figure 4-13
t
IDM -FAST
14T
—
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
t
IG
18T
—
ns
Figure 4-13
t
IG -FAST
14T
—
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State
4
t
IRI
22T
—
ns
Figure 4-14
t
IRI -FAST
18T
—
Delay from IRQA Assertion (exiting Stop) to External
Data Memory
5
5.
The interrupt instruction fetch is visible on the pins only in Mode 3.
t
IW
1.5T
—
ns
Figure 4-15
Delay from IRQA Assertion (exiting Wait) to External
Data Memory
Fast
6
Normal
7
6.
Fast stop mode:
Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery is
requested (OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery takes
one less cycle and t
clk
will continue same value it had before stop mode was entered.
t
IF
18T
22ET
—
—
ns
ns
Figure 4-15
RSTO pulse width
8
normal operation
internal reset mode
t
RSTO
128ET
8ET
—
—
—
—
Figure 4-16
相關(guān)PDF資料
PDF描述
DSP56858FVE 16-bit Digital Signal Controllers
DSP56858VF120 16-bit Digital Signal Controllers
DSP5685XEVMUM Feature Phone Software Application Product Brief
DSP5685XUM Feature Phone Software Application Product Brief
DSP56F800ERM Feature Phone Software Application Product Brief
相關(guān)代理商/技術(shù)參數(shù)
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DSP5685XEVMUM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Feature Phone Software Application Product Brief
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