參數(shù)資料
型號(hào)： DSP56321VL220
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： 24-Bit Digital Signal Processor
中文描述： 24位數(shù)字信號(hào)處理器
文件頁數(shù)： 23/84頁
文件大?。?/td> 898K
代理商： DSP56321VL220
AC Electrical Characteristics
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor
2-3
2.4 AC Electrical Characteristics
The timing waveforms shown in the AC electrical characteristics section are tested with a V
IL
maximum of 0.3 V
and a V
IH
minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown in Notes 7
and 9 of the previous table. AC timing specifications, which are referenced to a device input signal, are measured in
production with respect to the 50 percent point of the respective input signal’s transition. DSP56321 output levels
are measured with the production test machine V
OL
and V
OH
reference levels set at 0.4 V and 2.4 V, respectively.
Note:
Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test conditions are 16
MHz and rated speed with the DPLL enabled.
2.4.1
Internal Clocks
Internal supply current:
In Normal mode
3
— at 200 MHz
— at 220 MHz
— at 240 MHz
— at 275 MHz
In Wait mode
4
In Stop mode
5
Input capacitance
6
I
CCI
I
CCW
I
CCS
C
IN
—
—
—
—
—
—
190
200
210
235
25
15
—
—
—
—
—
—
mA
mA
mA
mA
mA
mA
—
—
10
pF
Notes:
1.
Power-up sequence: During power-up, and throughout the DSP56321 operation, V
CCQH
voltage must always be higher or
equal to V
CCQL
voltage.
Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC, and MODD/IRQD pins.
Section 4.3
provides a formula to compute the estimated current requirements in Normal mode. To obtain these results, all
inputs must be terminated (that is, not allowed to float). Measurements are based on synthetic intensive DSP benchmarks (see
Appendix A
). The power consumption numbers in this specification are 90 percent of the measured results of this benchmark.
This reflects typical DSP applications.
To obtain these results, all inputs must be terminated (that is, not allowed to float).
To obtain these results, all inputs not disconnected at Stop mode must be terminated (that is, not allowed to float), and the
DPLL and on-chip crystal oscillator must be disabled.
Periodically sampled and not 100 percent tested.
V
CCQH
= 3.3 V
±
0.3 V, V
CQLC
= 1.6 V
±
0.1 V; T
J
= –40°C to +100 °C, C
L
= 50 pF
This characteristic does not apply to XTAL.
Driving EXTAL to the low V
IHX
or the high V
ILX
value may cause additional power consumption (DC current). To minimize
power consumption, the minimum V
IHX
should be no lower than
0.9
×
V
CCQH
and the maximum V
ILX
should be no higher than 0.1
×
V
CCQH
.
2.
3.
4.
5.
6.
7.
8.
9.
Table 2-4.
Internal Clocks
Characteristics
Symbol
Expression
Min
Typ
Max
Internal operating frequency
With DPLL disabled
With DPLL enabled
f
—
—
Ef/2
(Ef
×
MF)/(PDF
×
DF)
—
—
Internal clock cycle time
With DPLL disabled
With DPLL enabled
T
C
—
—
2
×
ET
C
ET
C
×
PDF
×
DF/MF
—
—
Internal clock high period
With DPLL disabled
With DPLL enabled
T
H
—
0.49
×
T
C
ET
C
—
—
0.51
×
T
C
Table 2-3.
DC Electrical Characteristics
7
Characteristics
Symbol
Min
Typ
Max
Unit
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