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參數(shù)資料
型號： DSP56303VL100B1
廠商： Freescale Semiconductor
文件頁數(shù)： 55/108頁
文件大?。?/td> 0K
描述： IC DSP 24BIT 100MHZ 196-BGA
標(biāo)準(zhǔn)包裝： 630
系列： DSP563xx
類型： 定點(diǎn)
接口： 主機(jī)接口，SSI，SCI
時(shí)鐘速率： 100MHz
非易失內(nèi)存： ROM（576 B）
芯片上RAM： 24kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 196-LBGA
供應(yīng)商設(shè)備封裝： 196-MAPBGA（15x15）
包裝： 托盤
DSP56303 Technical Data, Rev. 11
2-30
Freescale Semiconductor
Specifications
2.5.6
Host Interface Timing
Table 2-16.
Host Interface Timings1,2,12
No.
Characteristic10
Expression
100 MHz
Unit
Min
Max
317
Read data strobe assertion width
5
HACK assertion width
TC + 9.9
19.9
—
ns
318
Read data strobe deassertion width5
HACK deassertion width
9.9
—
ns
319
Read data strobe deassertion width5 after “Last Data Register” reads8,11, or
between two consecutive CVR, ICR, or ISR reads3
HACK deassertion width after “Last Data Register” reads
8,11
2.5
× T
C + 6.6
31.6
—
ns
320
Write data strobe assertion width6
13.2
—ns
321
Write data strobe deassertion width8
HACK write deassertion width
after ICR, CVR and “Last Data Register” writes
after IVR writes, or
after TXH:TXM:TXL writes (with HLEND= 0), or
after TXL:TXM:TXH writes (with HLEND = 1)
2.5
× TC + 6.6
31.8
16.5
—
ns
322
HAS assertion width
9.9
—
ns
323
HAS deassertion to data strobe assertion
4
0.0
—
ns
324
Host data input setup time before write data strobe deassertion6
9.9
—
ns
325
Host data input hold time after write data strobe deassertion6
3.3
—
ns
326
Read data strobe assertion to output data active from high impedance
5
HACK assertion to output data active from high impedance
3.3
—
ns
327
Read data strobe assertion to output data valid5
HACK assertion to output data valid
—24.5
ns
328
Read data strobe deassertion to output data high impedance5
HACK deassertion to output data high impedance
—9.9
ns
329
Output data hold time after read data strobe deassertion
5
Output data hold time after HACK deassertion
3.3
—
ns
330
HCS assertion to read data strobe deassertion5
TC + 9.9
19.9
—
ns
331
HCS assertion to write data strobe deassertion
6
9.9
—
ns
332
HCS assertion to output data valid
—19.3
ns
333
HCS hold time after data strobe deassertion4
0.0
—
ns
334
Address (HAD[0–7]) setup time before HAS deassertion (HMUX=1)
4.6
—
ns
335
Address (HAD[0–7]) hold time after HAS deassertion (HMUX=1)
3.3
—
ns
336
HA[8–10] (HMUX=1), HA[0–2] (HMUX=0), HR/W setup time before data strobe
assertion
4
Read
Write
0
4.6
—
ns
337
HA[8–10] (HMUX=1), HA[0–2] (HMUX=0), HR/W hold time after data strobe
deassertion4
3.3
—
ns
338
Delay from read data strobe deassertion to host request assertion for “Last Data
Register” read
5, 7, 8
TC + 5.3
15.3
—
ns
339
Delay from write data strobe deassertion to host request assertion for “Last Data
Register” write6, 7, 8
1.5
× T
C + 5.3
20.3
—
ns
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