參數(shù)資料
型號: DSM2180F390K6
廠商: 意法半導(dǎo)體
元件分類: 數(shù)字信號處理
英文描述: DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (5V Supply)
中文描述: 帝斯曼(數(shù)字信號處理器系統(tǒng)內(nèi)存)模擬器件公司的ADSP - 218X系列(5V電源)
文件頁數(shù): 50/63頁
文件大?。?/td> 809K
代理商: DSM2180F390K6
DSM2180F3
50/63
Table 28. CPLD Macrocell Synchronous Clock Mode Timing
Note: 1. Fast Slew Rate output available on PB3-PB0, and PD2-PD0.
2. CLKIN (PD1) t
CLCL
= t
CH
+ t
CL
.
Table 29. CPLD Macrocell Asynchronous Clock Mode Timing
Symbol
Parameter
Conditions
-90
Fast PT
Aloc
Turbo
Off
Slew
Rate
1
Unit
Min
Max
f
MAX
Maximum Frequency
External Feedback
1/(t
S
+t
CO
)
30.30
MHz
Maximum Frequency
Internal Feedback
(f
CNT
)
1/(t
S
+t
CO
–10)
43.48
MHz
Maximum Frequency
Pipelined Data
1/(t
CH
+t
CL
)
50.00
MHz
t
S
Input Setup Time
15
Add 2
Add 10
ns
t
H
Input Hold Time
0
ns
t
CH
Clock High Time
Clock Input
10
ns
t
CL
Clock Low Time
Clock Input
10
ns
t
CO
Clock to Output Delay
Clock Input
18
Sub 2
ns
t
ARD
CPLD Array Delay
Any Macrocell
16
Add 2
ns
t
MIN
Minimum Clock Period
2
t
CH
+t
CL
20
ns
Symbol
Parameter
Conditions
-90
PT
Aloc
Turbo
Off
Slew
Rate
Unit
Min
Max
f
MAXA
Maximum Frequency
External Feedback
1/(t
SA
+t
COA
)
26.32
MHz
Maximum Frequency
Internal Feedback
(f
CNTA
)
1/(t
SA
+t
COA
–10)
35.71
MHz
Maximum Frequency
Pipelined Data
1/(t
CHA
+t
CLA
)
41.67
MHz
t
SA
Input Setup Time
8
Add 2
Add 10
ns
t
HA
Input Hold Time
12
ns
t
CHA
Clock Input High Time
12
Add 10
ns
t
CLA
Clock Input Low Time
12
Add 10
ns
t
COA
Clock to Output Delay
30
Add 10
Sub 2
ns
t
ARDA
CPLD Array Delay
Any Macrocell
16
Add 2
ns
t
MINA
Minimum Clock Period
1/f
CNTA
28
ns
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