參數(shù)資料
型號(hào): DSD1793DBR
元件分類: DAC
英文描述: 24 BIT 192 KHZ SAMPLING ADVANCED SEGMENT AUDIO STEREO DIGITAL TO ANALOG CONVERTER
中文描述: 24位192千赫采樣高級(jí)分段音頻立體聲數(shù)模轉(zhuǎn)換器
文件頁(yè)數(shù): 14/47頁(yè)
文件大小: 428K
代理商: DSD1793DBR
DSD1793
SLES075A MARCH 2003 REVISED JANUARY 2004
www.ti.com
21
Write Register
A master can write to any DSD1793 registers using single or multiple accesses. The master sends a DSD1793 slave
address with a write bit, a register address, and the data. If multiple access is required, the address is that of the
starting register, followed by the data to be transferred. When the data are received properly, the index register is
incremented automatically by 1. When the index register reaches 0x7F, the next value is 0x0. When undefined
registers are accessed, the DSD1793 does not send an acknowledgement. Figure 29 is a diagram of the write
operation.
Transmitter
M
S
M
S
M
S
M
S
S
M
Data Type
St
Slave
address
W
ACK
Register
address
ACK
Write data 1
ACK
Write data 2
ACK
ACK
Sp
M: Master device
S: Slave device
St: Start condition
ACK: Acknowledge
Sp: Stop condition
W: Write
Figure 29. Write Operation
Read Register
A master can read the DSD1793 register. The value of the register address is stored in an indirect index register in
advance. The master sends a DSD1793 slave address with a read bit after storing the register address. Then the
DSD1793 transfers the data which the index register points to. When the data are transferred during a multiple
access, the index register is incremented by 1 automatically. (When first going into read mode immediately following
a write, the index register is not incremented. The master can read the register that was previously written.) When
the index register reaches 0x7F, the next value is 0x0. The DSD1793 outputs some data when the index register is
0x10 to 0x1F, even if it is not defined in Table 4. Figure 30 is a diagram of the read operation.
Transmitter
M
S
M
S
M
S
M
M
Data Type
St
Slave
address
W
ACK
Register
address
ACK
Sr
Slave
address
R
ACK
Data
ACK
NACK
Sp
M: Master device
S: Slave device
St: Start condition
Sr: Repeated start condition
ACK: Acknowledge
Sp: Stop condition
NACK: Not Acknowledge
W: Write
R: Read
NOTE: The slave address after the repeat start condition must be the same as the previous slave address.
Figure 30. Read Operation
Noise Suppression
The DSD1793 incorporates noise suppression using the system clock (SCK). However, there must be no more than
two noise spikes in 600 ns. The noise suppression works for SCK frequencies between 8 MHz and 40 MHz in fast
mode. However, it works incorrectly in the particular following conditions.
Case 1:
1.
t(SCK) > 120 ns (t(SCK): period of SCK)
2.
t(HI) + t(DHD) < t(SCK) × 5
3.
Spike noise exists on the first half of the SCL HIGH pulse.
4.
Spike noise exists on the SDA HIGH pulse just before SDA goes LOW.
SCL
SDA
Noise
When these conditions occur at the same time, the data is recognized as LOW.
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