參數(shù)資料
型號: DSD1792ADBG4
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: SERIAL INPUT LOADING, 24-BIT DAC, PDSO28
封裝: GREEN, PLASTIC, TSSOP-28
文件頁數(shù): 17/57頁
文件大?。?/td> 634K
代理商: DSD1792ADBG4
DSD1792A
SLES106B FEBRUARY 2004 REVISED NOVEMBER 2006
www.ti.com
24
DME: Digital De-Emphasis Control
This bit is available for read and write.
Default value: 0
DME = 0
De-emphasis disabled (default)
DME = 1
De-emphasis enabled
The DME bit is used to enable or disable the de-emphasis function for both channels.
MUTE: Soft Mute Control
This bit is available for read and write.
Default value: 0
MUTE = 0
MUTE disabled (default)
MUTE = 1
MUTE enabled
The MUTE bit is used to enable or disable the soft mute function for both channels.
Soft mute is operated as a 256-step attenuator. The speed for each step to –
∞ dB (mute) is determined by the attenuation
rate selected in the ATS register.
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 19
R/W
0
1
0
1
REV
ATS1
ATS0
OPE
ZOE
DFMS
FLT
INZD
R/W: Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
REV: Output Phase Reversal
This bit is available for read and write.
Default value: 0
REV = 0
Normal output (default)
REV = 1
Inverted output
The REV bit is used to invert the output phase for both channels.
ATS[1:0]: Attenuation Rate Select
These bits are available for read and write.
Default value: 00
ATS[1:0]
Attenuation Rate Selection
00
PLRCK/1 (default)
01
PLRCK/2
10
PLRCK/4
11
PLRCK/8
The ATS[1:0] bits are used to select the rate at which the attenuator is decremented/incremented during level transitions.
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