參數(shù)資料
型號(hào): DSD1792
元件分類: DAC
英文描述: 24 bit 192 khz SAMPLING ADVANCED SEGMENT AUDIO STEREO DIGITAL TO ANALOG CONVERTER
中文描述: 24位192千赫采樣高級(jí)分段音頻立體聲數(shù)模轉(zhuǎn)換器
文件頁(yè)數(shù): 15/56頁(yè)
文件大?。?/td> 497K
代理商: DSD1792
SLES067A MARCH 2003 REVISED AUGUST 2003
www.ti.com
15
SYSTEM CLOCK AND RESET FUNCTIONS
System Clock Input
The DSD1792 requires a system clock for operating the digital interpolation filters and advanced segment DAC modulators.
The system clock is applied at the SCK input (pin 7). The DSD1792 has a system clock detection circuit that automatically
senses if the system clock is operating between 128 f
S
and
768 f
S
. Table 1 shows examples of system clock frequencies
for common audio sampling rates. If the oversampling rate of the delta-sigma modulator is selected as 128 f
S
, the system
clock frequency is over 256 f
S
.
Figure 24 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock
source with low phase jitter and noise. One of the Texas Instruments’ PLL1700 family of multiclock generators is an
excellent choice for providing the DSD1792 system clock.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SAMPLING FREQUENCY
SYSTEM CLOCK FREQUENCY (FSCK) (MHZ)
192 fS
256 fS
6.144
8.192
128 fS
4.096
384 fS
12.288
512 fS
16.384
768 fS
24.576
32 kHz
44.1 kHz
5.6488
8.4672
11.2896
16.9344
22.5792
33.8688
48 kHz
6.144
9.216
12.288
18.432
24.576
36.864
96 kHz
12.288
18.432
24.576
36.864
49.152
(1)
73.728
(1)
192 kHz
24.576
36.864
49.152
73.728
(1)This system clock rate is not supported for the given sampling frequency.
t(SCKH)
t(SCY)
System Clock (SCK)
t(SCKL)
2.0 V
0.8 V
H
L
PARAMETERS
MIN
13
MAX
UNITS
ns
t(SCY)
t(SCKH)
t(SCKL)
System clock pulse cycle time
System clock pulse duration, HIGH
0.4 (SCY)
0.4 (SCY)
ns
System clock pulse duration, LOW
ns
Figure 24. System Clock Input Timing
Power-On and External Reset Functions
The DSD1792 includes a power-on reset function. Figure 25 shows the operation of this function. With V
DD
> 2 V, the
power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time
V
DD
> 2 V. After the initialization period, the DSD1792 is set to its default reset state, as described in the
MODE CONTROL
REGISTERS
section of this data sheet.
The DSD1792 also includes an external reset capability using the RST input (pin 14). This allows an external controller
or master reset circuit to force the DSD1792 to initialize to its default reset state.
Figure 26 shows the external reset operation and timing. The
RST
pin is set to logic 0 for a minimum of 20 ns. The
RST
pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock periods.
Operation of the external reset is the same as that of the power-on reset. The external reset is especially useful in
applications where there is a delay between the DSD1792 power up and system clock activation.
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