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參數(shù)資料
| 型號(hào)： | DSC-11520-393 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | DIGITAL TO SYNCHRO OR RESOLVER, DMA36 |
| 封裝： | 0.780 X 1.900 INCH, 0.210 INCH HEIGHT, DOUBLE WIDTH, KOVAR, DIP-36 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大小： | 159K |
| 代理商： | DSC-11520-393 |
5
Data Device Corporation
www.ddc-web.com
DSC-11520
L-05/05-0
DSC-11520 outputs down to the nominal 11.8 V and 6.81 V lev-
els stated above, or to lower voltages if desired. The magnitude
of the resistors R' in ohms is calculated as follows:
5000
NOMINAL L-L VOLTAGE LEVEL
R' =
(VR - 1.3)
(
)
1.3
DESIRED L-L VOLTAGE LEVEL
OUTPUT PHASING AND OUTPUT SCALE FACTOR
The analog output signals have the following phasing:
Synchro output
S1 — S3 = (RH-RL) Ao (1 + A(θ)) sin θ
S3 — S2 = (RH-RL) Ao (1 + A(θ)) sin (θ + 120°)
S2 — S1 = (RH-RL) Ao (1 + A(θ)) sin (θ + 240°)
Resolver output
S1 — S3 = (RH-RL) Ao (1 + A(θ)) sin θ
S2 — S4 = (RH-RL) Ao (1 + A(θ)) cos θ
The output amplitudes simultaneously track reference voltage
fluctuations because they are proportional to (RH-RL). The trans-
formation ratio Ao is 11.8/26 for 11.8 V rms L-L output. The max-
imum variation in Ao from all causes is ±0.2%. The term A (θ)
represents the variation of the amplitude with the digital input
angle. A (
θ), which is called the scale factor variation, is a smooth
function of
θ without discontinuities and is less than ±0.1% for all
values of
θ. The total maximum variation in Ao (1 + A(θ)) is there-
fore ±0.3%.
Because the amplitude factor (RH-RL) Ao (1 + A(θ)) varies simul-
taneously on all output lines, it will not be a source of error when
the DSC-11520 is to drive a ratiometric system such as a syn-
chro or resolver. However, if the outputs are used independently,
as in X-Y plotters, the amplitude variations must be taken into
account.
FIGURE 3B. LL,LM,LA TIMING DIAGRAM (8-BIT)
1.895 ±0.005
(48.1 ±0.13)
1.700 ±0.005
(43.2 ±0.13)
0.018 (0.46)
DIAM TYP
0.100 TYP(2.54)
TOL. NON-
CUMULATIVE
0.21 MAX
(5.3)
DOT
IDENTIFIES
PIN 1
0.775 ±0.005
(19.7 ±0.13)
0.600 ±0.005
(15.2 ±0.13)
0.09 ±0.01
(2.3 ±0.25)
0.10 ±0.01
(2.5 ±0.3)
SIDE VIEW
BOTTOM VIEW
0.25 MIN
(6.4)
0.015 MAX
(0.39)
SEATING
PLANE
0.055 (1.4)
RAD TYP
0.086 TYP
RADIUS
1. Dimensions shown are in inches (millimeters).
NOTES:
2. Lead identification numbers are for reference only.
3. Lead cluster shall be centered within ± 0.10 of outline
dimensions. Lead spacing dimensions apply only at
seating plane.
4. Pin material meets solderability requirements of
MIL-STD-202E, Method 208C.
5. Package is Kovar with electroless nickel plating.
6. Case is electrically floating.
35
S3
36
S2
33
S2'
DSC-11520
+SIN
32
S1
36
S2
33
S2'
35
S3
34
S3'
DSC-11520
S1
S2
S3
+COS
SYNCHRO OUTPUT
RESOLVER OUTPUT
FIGURE 4. OUTPUT PIN PROGRAMMING
Notes:
1.-R (PIN 7) can be used for test purposes to detect whether a reference signal
is present. See block diagram.
2. Functions LL, LA and LM may be left unconnected when not used.
TABLE 2. PIN CONNECTIONS
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
NC
+15 V
GND
-15 V
NC
-R
RL
RL'
RH
RH'
BIT 14
13
14
15
16
17
18
19
20
21
22
23
24
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
25
26
27
28
29
30
31
32
33
34
35
36
BIT 1 (MSB)
BIT 15
BIT 16 (LSB)
LM
LL
LA
NC
S1
S2'
S3'
S3 (+SIN)
S2 (+COS)
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| DSC-11524 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital to Synchro Conversion|15 mA DRIVE. 11.8V L-L? SYNCHRO / RESOLVER OUTPUTS |
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