參數(shù)資料
型號(hào): DS90LV110TMTC
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 時(shí)鐘及定時(shí)
英文描述: 1 to 10 LVDS Data/Clock Distributor
中文描述: 90LV SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
封裝: TSSOP-28
文件頁(yè)數(shù): 3/9頁(yè)
文件大?。?/td> 468K
代理商: DS90LV110TMTC
Electrical Characteristics
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
SUPPLY CURRENT
I
CCD
Parameter
Conditions
Min
Typ
Max
Units
Total Supply Current
R
L
= 100
, C
L
= 5 pF, 400 MHz,
EN = High
No Load, 400 MHz, EN = High
EN = Low
125
195
mA
80
15
125
29
mA
mA
I
CCZ
TRI-STATE Supply Current
Note 1:
“Absolute Maximum Ratings” are these beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should
be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
Note 2:
All typical are given for V
CC
= +3.3V and T
A
= +25C, unless otherwise stated.
Note 3:
V
OS
is defined as (V
OH
+ V
OL
) / 2.
Note 4:
Only one output can be shorted at a time. Don’t exceed the package absolute maximum rating.
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
T
LHT
Parameter
Conditions
Min
Typ
390
Max
550
Units
ps
Output Low-to-High Transition Time, 20% to 80%, Figure 4
(Note 5)
Output High-to-Low Transition Time, 80% to 20%, Figure 4
(Note 5)
LVDS Data Jitter, Deterministic
(Peak-to-Peak)(Note 6)
LVDS Clock Jitter, Random (Note 6)
T
HLT
390
550
ps
T
DJ
V
ID
= 300mV; PRBS=2
23
-1 data;
V
CM
= 1.2V at 800 Mbps (NRZ)
V
ID
= 300mV; V
CM
= 1.2V
at 400 MHz clock
145
ps
T
RJ
2.8
ps
T
PLHD
T
PHLD
T
SKEW
T
CCS
T
PHZ
T
PLZ
T
PZH
T
PZL
Propagation Low to High Delay, Figure 5
Propagation High to Low Delay, Figure 5
Pulse Skew |T
PLHD
- T
PHLD
| (Note 5)
Output Channel-to-Channel Skew, Figure 6 (Note 5)
Disable Time (Active to TRI-STATE) High to Z, Figure 1
Disable Time (Active to TRI-STATE) Low to Z, Figure 1
Enable Time (TRI-STATE to Active) Z to High, Figure 1
Enable Time (TRI-STATE to Active) Z to Low, Figure 1
2.2
2.2
2.8
2.8
20
35
3.0
1.8
10.0
7.0
3.6
3.6
340
91
6.0
6.0
23.0
23.0
ns
ns
ps
ps
ns
ns
ns
ns
Note 5:
The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage and
temperature) range.
Note 6:
The measurement used the following equipment and test setup: HP8133A pattern/pulse generator), 5 feet of RG-142 cable with DUT test board and
HP83480A (digital scope mainframe) with HP83484A (50GHz scope module). The HP8133A with the RG-142 cable exhibit a T
DJ
= 26ps and T
RJ
= 1.3 ps
D
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