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參數(shù)資料
| 型號(hào)： | DS90CF363BMTX/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 1/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPD-LINK 18BIT TX 48-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 發(fā)射器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 21/3 |
| 規(guī)程： | FPD 鏈路，LVDS |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | DS90CF363BMTX |
SNLS180D – JULY 2004 – REVISED APRIL 2013
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz
Check for Samples: DS90CF363B
1
FEATURES
345 mV (typ) Swing LVDS Devices for Low EMI
PLL Requires no External Components
2
No Special Start-up Sequence Required
between Clock/Data and /PD Pins. Input Signal
Compatible with TIA/EIA-644 LVDS Standard
(Clock and Data) can be Applied Either Before
Low Profile 48-lead TSSOP Package
or After the Device is Powered.
Improved Replacement for:
Support Spread Spectrum Clocking up to
–
SN75LVDS84, DS90CF363A
100KHz Frequency Modulation & Deviations of
±2.5% Center Spread or
5% Down Spread.
DESCRIPTION
"Input Clock Detection" Feature will Pull all
The DS90CF363B transmitter converts 21 bits of
LVDS Pairs to Logic Low when Input Clock is
CMOS/TTL data into three LVDS (Low Voltage
Missing and when /PD Pin is Logic High.
Differential Signaling) data streams. A phase-locked
transmit clock is transmitted in parallel with the data
18 to 68 MHz Shift Clock Support
streams over a fourth LVDS link. Every cycle of the
Best–in–Class Set & Hold Times on TxINPUTs
transmit clock 21 bits of input data are sampled and
Tx Power Consumption < 130 mW (typ)
transmitted. At a transmit clock frequency of 65 MHz,
@65MHz Grayscale
18 bits of RGB data and 3 bits of LCD timing and
control
data
(FPLINE,
FPFRAME,
DRDY)
are
40% Less Power Dissipation than BiCMOS
transmitted at a rate of 455 Mbps per LVDS data
Alternatives
channel. Using a 65 MHz clock, the data throughput
Tx Power-Down Mode < 37
μW (typ)
is 170 Mbytes/sec. The DS90CF363B is fixed as a
Supports VGA, SVGA, XGA and Dual Pixel
Falling edge strobe transmitter and will interoperate
SXGA.
with a Falling edge strobe Receiver (DS90CF366)
without any translation logic.
Narrow Bus Reduces Cable Size and Cost
Up to 1.3 Gbps Throughput
This chipset is an ideal means to solve EMI and
cable size problems associated with wide, high speed
Up to 170 Megabytes/sec Bandwidth
TTL interfaces.
Block Diagram
Figure 1. DS90CF363B
See Package Number DGG0048A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright 2004–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS90CF363MTD | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:+3.3V LVDS Transmitter 18-Bit Flat Panel Display (FPD) LinkΑ65 MHz |
| DS90CF363MTDX | 功能描述:IC TX PROG LVDS 3.3V 48-TSSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| DS90CF364 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) LinkΑ65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) LinkΑ65 MHz |
| DS90CF364A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| DS90CF364A_07 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-65MHz |
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