參數(shù)資料
型號(hào): DS89C450-QNG+
廠(chǎng)商: Maxim Integrated Products
文件頁(yè)數(shù): 33/46頁(yè)
文件大小: 0K
描述: IC MCU FLASH 64KB 25MHZ 44-PLCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 26
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: EBI/EMI,SIO,UART/USART
外圍設(shè)備: 電源故障復(fù)位,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 64KB(64K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線(xiàn))
包裝: 管件
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers
39 of 46
Figure 14. System Clock Sources
4X/2X
CTM
CRYSTAL
OSCILLATOR
DIVIDE 1024
RING
OSCILLATOR
CLOCK
MULTIPLIER
CD0
CD1
SELECTOR
RING
ENABLE
MUX
SYSTEM
CLOCK
Bandgap-Monitored Interrupt and Reset Generation
The power monitor in the DS89C430 monitors the VCC pin in relation to the on-chip bandgap voltage reference.
Whenever VCC falls below VPFW, an interrupt is generated if the corresponding power-fail interrupt-enable bit EPFI
(WDCON.5) is set, causing the device to vector to address 33h. The power-fail interrupt status bit PFI (WDCON.4)
is set any time VCC transitions below VPFW, and can only be cleared by software once set. Similarly, as VCC falls
below VRST, a reset is issued internally to halt program execution. Following power-up, a power-on reset initiates a
power-on reset timeout before starting program execution. When VCC is first applied to the DS89C430, the
processor is held in reset until VCC > VRST and a delay of 65,536 oscillator cycles has elapsed, to ensure that power
is within tolerance and the clock source has had time to stabilize. Once the reset timeout period has elapsed, the
reset condition is removed automatically and software execution begins at the reset vector location of 0000h. The
power-on reset flag POR (WDCON.6) is set to logic 1 to indicate a power-on reset has occurred, and can only be
cleared by software.
When the DS89C430 enters stop mode, the bandgap, reset comparator, and power-fail interrupt comparator are
automatically disabled to conserve power if the BGS (EXIF.0) bit is set to logic 0. This is the lowest power mode. If
BGS is set to logic 1, the bandgap reference, reset comparator, and the power-fail comparator are powered up,
although in a mode that reduces their power consumption.
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DS89LV21TN 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Transceiver