參數(shù)資料
型號: DS89C420-ECL
英文描述: Ultra-High-Speed Microcontroller
中文描述: 超高速微控制器
文件頁數(shù): 38/59頁
文件大?。?/td> 539K
代理商: DS89C420-ECL
DS89C420
38 of 59
the multiplier startup counter. During the multiplier startup period the CKRY bit remains cleared and the
CD1 and CD0 clock controls cannot be set to 00b. The CTM bit is cleared to a logic 0 on all resets.
Figure 11 gives a simplified diagram of the generation of the system clocks. Specifics of hardware
restrictions associated with the use of the 4X/
X
2
CTM, CKRY, CD1, and CD0 bits are outlined in the
SFR description.
Figure 11. System Clock Sources
4X/2X
CTM
Crystal
Oscillator
Divide 1024
Ring
Oscillator
Clock
Multiplier
CD0
CD1
Selector
Ring
Enable
MUX
System
Clock
Bandgap-Monitored Interrupt and Reset Generation
The power monitor in the DS89C420 monitors the V
CC
pin in relation to the on-chip bandgap voltage
reference. Whenever V
CC
falls below V
PFW
, an interrupt is generated if the corresponding power-fail
interrupt-enable bit EPFI (WDCON.5) is set, causing the device to vector to address 33h. The power-fail
interrupt-status bit PFI (WDCON.4) is set anytime V
CC
transitions below V
PFW
, and can only be cleared
by software once set. Similarly, as V
CC
falls below V
RST
, a reset is issued internally to halt program
execution. Following power-up, a power-on reset initiates a power-on reset timeout before starting
program execution. When V
CC
is first applied to the DS89C420, the processor is held in reset until
V
CC
> V
RST
and a delay of 65,536 oscillator cycles has elapsed, to ensure that power is within tolerance
and the clock source has had time to stabilize. Once the reset timeout period has elapsed, the reset
condition is removed automatically and software execution begins at the reset vector location of 0000h.
The power-on reset flag POR (WDCON.6) is set to logic 1 to indicate a power-on reset has occurred, and
can only be cleared by software.
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相關代理商/技術參數(shù)
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