• 參數(shù)資料
    型號: DS83C530
    廠商: Maxim Integrated Products, Inc.
    英文描述: EPROM/ROM Micro with Real Time Clock(帶實時時鐘的EPROM/ROM高速微控制器)
    中文描述: EPROM微控制器,帶有實時時鐘
    文件頁數(shù): 23/41頁
    文件大?。?/td> 437K
    代理商: DS83C530
    DS87C530/DS83C530
    070898 23/41
    WATCHDOG TIME–OUT VALUES
    Table 8
    INTERRUPT
    WD1
    0
    WD0
    0
    TIME–OUT
    2
    17
    clocks
    2
    20
    clocks
    2
    23
    clocks
    2
    26
    clocks
    TIME (33 MHz)
    3.9718 ms
    RESET TIME–OUT
    2
    17
    + 512 clocks
    2
    20
    + 512 clocks
    2
    23
    + 512 clocks
    2
    26
    + 512 clocks
    TIME (33 MHz)
    3.9874 ms
    0
    1
    31.77 ms
    31.79 ms
    1
    0
    254.20 ms
    254.21 ms
    1
    1
    2033.60 ms
    2033.62 ms
    As shown above, the Watchdog Timer uses the crystal
    frequency as a time base. A user selects one of four
    counter values to determine the time–out. These clock
    counter lengths are 2
    17
    = 131,072 clocks; 2
    20
    =
    1,048,576; 2
    23
    = 8,388,608 clocks; and 2
    26
    =
    67,108,864 clocks. The times shown in Table 8 above
    are with a 33 MHz crystal frequency. Once the counter
    chain has completed a full interrupt count, hardware will
    set an interrupt flag. Regardless of whether the user
    enables this interrupt, there are then 512 clocks left until
    the reset flag is set. Software can enable the interrupt
    and reset individually. Note that the Watchdog is a free
    running timer and does not require an enable.
    There are five control bits in special function registers
    that affect the Watchdog Timer and two status flags that
    report to the user. WDIF (WDCON.3) is the interrupt flag
    that is set at timer termination when there are 512 clocks
    remaining until the reset flag is set. WTRF (WDCON.2)
    is the flag that is set when the timer has completely
    timed out. This flag is normally associated with a CPU
    reset and allows software to determine the reset source.
    EWT (WDCON.1) is the enable for the Watchdog timer
    reset function. RWT (WDCON.0) is the bit that software
    uses to restart the Watchdog Timer. Setting this bit
    restarts the timer for another full interval. Application
    software must set this bit before the time–out. Both of
    these bits are protected by Timed Access discussed
    below. As mentioned previously, WD1 and 0 (CKCON .7
    and 6) select the time–out. The Reset Watchdog Timer
    bit (WDCON.0) should be asserted prior to modifying
    the Watchdog Timer Mode Select bits (WD1, WD0) to
    avoid corruption of the watchdog count. Finally, the user
    can enable the Watchdog Interrupt using EWDI (EIE.4).
    The Special Function Register map is shown above.
    INTERRUPTS
    The DS87C530/DS83C530 provides 14 interrupt
    sources with three priority levels. The Power–fail Inter-
    rupt (PFI) has the highest priority. Software can assign
    high or low priority to other sources. All interrupts that
    are new to the 8051 family, except for the PFI, have a
    lower natural priority than the originals.
    INTERRUPT SOURCES AND PRIORITIES
    Table 9
    NAME
    PFI
    INT0
    TF0
    INT1
    TF1
    SCON0
    TF2
    SCON1
    INT2
    INT3
    INT4
    INT5
    WDTI
    RTCI
    DESCRIPTION
    Power Fail Interrupt
    External Interrupt 0
    Timer 0
    External Interrupt 1
    Timer 1
    TI0 or RI0 from serial port 0
    Timer 2
    TI1 or RI1 from serial port 1
    External Interrupt 2
    External Interrupt 3
    External Interrupt 4
    External Interrupt 5
    Watchdog Time–Out Interrupt
    Real Time Clock Interrupt
    VECTOR
    33h
    03h
    0Bh
    13h
    1Bh
    23h
    2Bh
    3Bh
    43h
    4Bh
    53h
    5Bh
    63h
    6Bh
    NATURAL
    PRIORITY
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    8051/DALLAS
    DALLAS
    8051
    8051
    8051
    8051
    8051
    8051
    DALLAS
    DALLAS
    DALLAS
    DALLAS
    DALLAS
    DALLAS
    DALLAS
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