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參數(shù)資料
型號： DS80C400-FNY+
廠商： Maxim Integrated Products
文件頁數(shù)： 6/97頁
文件大?。?/td> 0K
描述： IC MCU 75MHZ 16MB HP 100-LQFP
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 90
系列： 80C
核心處理器： 8051
芯體尺寸： 8-位
速度： 75MHz
連通性： 1 線，CAN，EBI/EMI，以太網(wǎng)，SIO，UART/USART
外圍設備： 電源故障復位，WDT
輸入/輸出數(shù)： 64
程序存儲器容量： 64KB（64K x 8）
程序存儲器類型： ROM
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 1.62 V ~ 3.6 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤
配用： DS80C400-KIT#-ND - EVAL KIT FOR DS80C400
其它名稱： DS80C400+FNY
DS80C400+FNY+
DS80C400+FNY+-ND
DS80C400+FNY-ND
DS80C400 Network Microcontroller
14 of 97
MOVX CHARACTERISTICS (NONMULTIPLEXED ADDRESS/DATA BUS) (Note 1)
(VCC3 = 3.0V to 3.6V, VCC1 = 1.8V +±10%, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
MIN
MAX
UNITS
STRETCH
VALUES
CST (MD2:0)
Input Instruction Float After PSEN
tPXIZ
2tCLCL - 5
ns
CST = 0
3tCLCL - 5
1≤ CST ≤ 3
11tCLCL - 5
4 ≤ CST ≤ 7
PSEN
High to Data Address, Port 4 CE,
Port 5 PCE Valid
tPHAV
tCHCL - 3
ns
RD
Pulse Width (P3.7 or PSEN)
tRLRH
2tCLCL - 5
ns
CST =0
(4 x CST) tCLCL - 3
1 ≤ CST ≤ 7
WR
Pulse Width (P3.6)
tWLWH
2tCLCL - 5
ns
CST =0
(4 x CST)tCLCL - 3
1 ≤ CST ≤ 7
RD
(P3.7 or PSEN) Low to Valid Data In
tRLDV
2tCLCL - 17
ns
CST = 0
(4 x CST)tCLCL - 17
1 ≤ CST ≤ 7
Data Hold After RD (P3.7 or PSEN) High
tRHDX
-2
ns
Data Float After RD (P3.7 or PSEN) High
tRHDZ
tCLCL - 5
ns
CST = 0
2tCLCL - 5
1≤ CST ≤ 3
6tCLCL - 5
4 ≤ CST ≤ 7
PSEN
High to WR Low
tPHWL
2tCLCL - 3
ns
CST = 0
3tCLCL - 3
1≤ CST ≤ 3
11tCLCL - 3
4 ≤ CST ≤ 7
PSEN
High to (RD or PSEN) Low
tPHRL
2tCLCL - 3
ns
CST = 0
3tCLCL - 3
1≤ CST ≤ 3
11tCLCL - 3
4 ≤ CST ≤ 7
Port 7 Address to Valid Data In
tAVDV1
3tCLCL - 19
ns
CST = 0
(4 x CST + 2)tCLCL- 19
1≤ CST ≤ 3
(4 x CST + 10)tCLCL -
19
4 ≤ CST ≤ 7
Port 2, 4, 6 Address, Port 4 CE or Port 5
PCE to Valid Data In
tAVDV2
3tCLCL + tCLCH - 19
ns
CST = 0
(4 x CST + 2)tCLCL +
tCLCH - 19
1≤ CST ≤ 3
(4 x CST + 10)tCLCL +
tCLCH - 19
4 ≤ CST ≤ 7
Port 7 Address to (RD or PSEN) or WR
Low
tAVWL1
tCLCL - 5
ns
CST = 0
2tCLCL - 5
1 ≤ CST ≤ 3
10tCLCL - 5
4 ≤ CST ≤ 7
Port 2, 4, 6 Address, Port 4 CE or Port 5
PCE to (RD or PSEN) or WR Low
tAVWL2
tCLCL + tCLCH - 5
ns
CST = 0
2tCLCL + tCLCH - 5
1 ≤ CST ≤ 3
10tCLCL + tCLCH - 5
4 ≤ CST ≤ 7
Data Valid to WR Transition
tQVWX
0
ns
Data Hold After WR High
tWHQX
tCLCL - 4
ns
CST = 0
2CLCL - 7
1 ≤ CST ≤ 3
6tCLCL - 7
4 ≤ CST ≤ 7
(RD or PSEN) or WR High to Port 4 CE
or Port 5 PCE High
tWHCEH
tCHCL - 5
tCHCL + 13
ns
CST = 0
tCLCL + tCHCL - 5
tCLCL + tCHCL +12
1 ≤ CST ≤ 3
5tCLCL + tCHCL -5
5tCLCL + tCHCL +12
4 ≤ CST ≤ 7
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: All parameters apply to both commercial and industrial temperature operation unless otherwise noted.
Note 3: CST is the stretch cycle value as determined by the MD2, MD1, and MD0 bits of the CKCON register. tCLCL, tCLCH, tCHCL are time periods
associated with the internal system clock and are related to the external clock. See the System Clock Time Periods table.
Note 4: All signals characterized with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. The following
signals, when configured for memory interface, are also characterized with 100pF loading: Port 4 (CE0-3, A16–A19), Port 5.4–5.7
(PCE0-3), Port 6.0–6.5 (CE4-7, A20, A2), Port 7 (demultiplexed mode A0–A7).
Note 5: References to the XTAL or CLK signal in timing diagrams is to assist in determining the relative occurrence of events, not for determing
absolute signal timing with respect to the external clock.
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DS80C400-FNY+ 功能描述:8位微控制器 -MCU Network MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
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