參數(shù)資料
型號: DS80C323-QCD
廠商: DALLAS SEMICONDUCTOR
元件分類: Microcontroller
英文描述: 8-BIT, MROM, 18 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 7/42頁
文件大?。?/td> 687K
代理商: DS80C323-QCD
DS80C320/DS80C323
15 of 42
As shown above, the watchdog timer uses the crystal frequency as a time base. A user selects one of four
counter values to determine the timeout. These clock counter lengths are 2
17 = 131,072 clocks; 220=
1,048,576; 2
23= 8,388,608 clocks; or 226= 67,108,864 clocks. The times shown in Table 4 are with a 25
MHz crystal frequency. Note that once the counter chain has reached a conclusion, the optional interrupt
is generated. Regardless of whether the user enables this interrupt, there are then 512 clocks left until a
reset occurs. There are 5 control bits in special function registers that affect the Watchdog Timer and two
status flags that report to the user. The Reset Watchdog Timer bit (WDCON.0) should be asserted prior to
modifying the Watchdog Timer Mode Select bits (WD1, WD0) to avoid corruption of the watchdog
count.
WDIF (WDCON.3) is the interrupt flag that is set when there are 512 clocks remaining until a reset
occurs. WTRF (WDCON.2) is the flag that is set when a Watchdog reset has occurred. This allows the
application software to determine the source of a reset.
Setting the EWT (WDCON.1) bit enables the Watchdog Timer. The bit is protected by Timed Access
discussed below. Setting the RWT (WDCON.0) bit restarts the Watchdog Timer for another full interval.
Application software must set this bit prior to the timeout. As mentioned previously, WD1 and 0
(CKCON .7 and 6) select the timeout. Finally, the Watchdog Interrupt is enabled using EWDI (EIE.4).
INTERRUPTS
The DS80C320/DS80C323 provides 13 sources of interrupt with three priority levels. The Power-fail
Interrupt (PFI), if enabled, always has the highest priority. There are two remaining user selectable
priorities: high and low. If two interrupts that have the same priority occur simultaneously, the natural
precedence given below determines which is a acted upon. Except for the PFI, all interrupts that are new
to the 8051 family have a lower natural priority than the originals.
INTERRUPT PRIORITY Table 5
NAME
DESCRIPTION
VECTOR
NATURAL PRIORITY
OLD/NEW
PFI
Power-fail Intterupt
33h
j
1
NEW
INT0
External Interrupt 0
03h
2
OLD
TF0
Timer 0
0Bh
3
OLD
INT1
External Interrupt 1
13h
4
OLD
TF1
Timer 1
1Bh
5
OLD
SCON0
TI0 or RI0 from serial port 0
23h
6
OLD
TF2
Timer 2
2Bh
7
OLD
SCON1
TI1 or RI1 from serial port 1
3Bh
8
NEW
INT2
External Interrupt 2
43h
9
NEW
INT3
External Interrupt 3
4Bh
10
NEW
INT4
External Interrupt 4
53h
11
NEW
INT5
External Interrupt 5
5Bh
12
NEW
WDTI
Watchdog Timeout Interrupt
63h
13
NEW
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