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DS80C320/DS80C323
110196 14/38
As shown above, the Watchdog Timer uses the crystal
frequency as a time base. A user selects one of four
counter values to determine the time–out. These clock
counter lengths are 2
17
= 131,072 clocks; 2
20
=
1,048,576; 2
23
= 8,388,608 clocks; or 2
26
= 67,108,864
clocks. The times shown in Table 4 above are with a
25 MHz crystal frequency. Note that once the counter
chain has reached a conclusion, the optional interrupt is
generated. Regardless of whether the user enables this
interrupt, there are then 512 clocks left until a reset
occurs. There are five control bits in special function
registers that affect the Watchdog Timer and two status
flags that report to the user.
WDIF (WDCON.3) is the interrupt flag that is set when
there are 512 clocks remaining until a reset occurs.
WTRF (WDCON.2) is the flag that is set when a Watch-
dog reset has occurred. This allows the application soft-
ware to determine the source of a reset.
EWT (WDCON.1) is the enable for the Watchdog Timer.
Software sets this bit to enable the timer. The bit is pro-
tected by Timed Access discussed below. RWT
(WDCON.0) is the bit that software uses to restart the
Watchdog Timer. Setting this bit restarts the timer for
another full interval. Application software must set this
bit prior to the time–out. As mentioned previously, WD1
and 0 (CKCON .7 and 6) select the time–out. Finally, the
Watchdog Interrupt is enabled using EWDI (EIE.4). The
Special Function Register map is shown below.
INTERRUPTS
The DS80C320/DS80C323 provides 13 sources of
interrupt with three priority levels. The Power–fail Inter-
rupt (PFI), if enabled, always has the highest priority.
There are two remaining user selectable priorities: high
and low. If two interrupts that have the same priority
occur simultaneously, the natural precedence given
below determines which is a acted upon. Except for the
PFI, all interrupts that are new to the 8051 family have a
lower natural priority than the originals.
INTERRUPT PRIORITY
Table 5
NAME
PFI
INT0
TF0
INT1
TF1
SCON0
TF2
SCON1
INT2
INT3
INT4
INT5
WDTI
DESCRIPTION
Power Fail Interrupt
External Interrupt 0
Timer 0
External Interrupt 1
Timer 1
TI0 or RI0 from serial port 0
Timer 2
TI1 or RI1 from serial port 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
Watchdog Time–out Interrupt
VECTOR
33h
03h
0Bh
13h
1Bh
23h
2Bh
3Bh
43h
4Bh
53h
5Bh
63h
NATURAL PRIORITY
1
2
3
4
5
6
7
8
9
10
11
12
13
OLD/NEW
NEW
OLD
OLD
OLD
OLD
OLD
OLD
NEW
NEW
NEW
NEW
NEW
NEW
POWER MANAGEMENT
The DS80C320/DS80C323 provides the standard Idle
and power–down (Stop) that are available on the stan-
dard 80C32. However the device has enhancements
that make these modes more useful, and allow more
power saving.
The Idle mode is invoked by setting the LSB of the
Power Control register (PCON – 87h). Idle will leave
internal clocks, serial port and timer running. No
memory access will be performed so power is dramati-
cally reduced. Since clocks are running, the Idle power
consumption is related to crystal frequency. It should be
approximately 1/2 of the operational power. The CPU
can exit the Idle state with any interrupt or a reset.
The power–down or Stop mode is invoked by setting the
PCON.1 bit. Stop mode is a lower power state than Idle
since it turns off all internal clocking. The I
CC
of a stan-
dard Stop mode is approximately 1
μ
A but is specified in
the Electrical Specifications. The CPU will exit Stop
mode from an external interrupt or a reset condition.