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DS80C310
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MOVX CHARACTERISTICS
VARIABLE CLOCK
PARAMETER
SYMBOL
MIN
MAX
UNITS
STRETCH
(Note 1)
1.5tCLCL-5
tMCS=0
Data Access ALE Pulse Width
tLHLL2
2tCLCL-5
ns
tMCS>0
0.5tCLCL-5
tMCS=0
Port 0 Address Valid to ALE Low
tAVLL2
tCLCL-5
ns
tMCS>0
0.5tCLCL-15
tMCS=0
Address Hold after ALE Low for
MOVX Write
tLLAX2
tCLCL-7
ns
tMCS>0
2tCLCL-5
tMCS=0
RD Pulse Width
tRLRH
tMCS-10
ns
tMCS>0
2tCLCL-5
tMCS=0
WR Pulse Width
tWLWH
tMCS-10
ns
tMCS>0
2tCLCL-20
tMCS=0
RD Low to Valid Data In
tRLDV
tMCS-20
ns
tMCS>0
Data Hold after Read
tRHDX
0
ns
tCLCL-5
tMCS=0
Data Float after Read
tRHDZ
2tCLCL-5
ns
tMCS>0
2.5tCLCL-28
tMCS=0
ALE Low to Valid Data In
tLLDV
tCLCL+tMCS-40
ns
tMCS>0
3tCLCL-22
tMCS=0
Port 0 Address to Valid Data In
tAVDV1
2.0tCLCL+ tMCS -
25
ns
tMCS>0
3.5tCLCL-35
tMCS=0
Port 2 Address to Valid Data In
tAVDV2
2.5tCLCL+ tMCS-
35
ns
tMCS>0
0.5tCLCL-14
0.5tCLCL+5
tMCS=0
ALE Low to
RD or WR Low
tLLWL
tCLCL-8
tCLCL+5
ns
tMCS>0
tCLCL-9
tMCS=0
Port 0 Address to
RD or WR Low
tAVWL1
2tCLCL-8
ns
tMCS>0
1.5tCLCL-10
tMCS=0
Port 2 Address to
RD or WR Low
tAVWL2
2.5tCLCL-10
ns
tMCS>0
Data Valid to
WR Transition
tQVWX
-14
ns
tCLCL-11
tMCS=0
Data Hold after Write
tWHQX
2tCLCL-10
ns
tMCS>0
RD Low to Address Float
tRLAZ
(Note 2)
ns
0
10
tMCS=0
RD or WR High to ALE High
tWHLH
tCLCL-5
tCLCL+9
ns
tMCS>0
Note 1:
tMCS is a time period related to the stretch memory cycle selection. The following table shows the value of tMCS for each
stretch selection.
M2
M1
M0
MOVX CYCLES
tMCS
0
2 machine cycles
0
1
3 machine cycles (default)
4 tCLCL
0
1
0
4 machine cycles
8 tCLCL
0
1
5 machine cycles
12 tCLCL
1
0
6 machine cycles
16 tCLCL
1
0
1
7 machine cycles
20 tCLCL
1
0
8 machine cycles
24 tCLCL
1
9 machine cycles
28 tCLCL