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參數(shù)資料
| 型號： | DS8007A-EAG+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 16/41頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE SMART CARD 48-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 應(yīng)用： | 智能卡 |
| 接口： | 并聯(lián) |
| 電源電壓： | 2.7 V ~ 6 V |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | 90-8007A+TAG |
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DS8007A
Multiprotocol Dual Smart Card Interface
______________________________________________________________________________________
23
UART Receive Register (URR)/UART Transmit Register (UTR)
R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to 00000000b on RIU = 0.
765
432
1
0
Address 0Dh
UR7/UT7
UR6/UT6
UR5/UT5
UR4/UT4
UR3/UT3
UR2/UT2
UR1/UT1
UR0/UT0
RW-0
FIFO Control Register (FCR)
R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to 0uuu0uuub on RIU = 0.
765
432
1
0
Address 0Ch
—
PEC2
PEC1
PEC0
FTE1
FL2
FL1
FL0
W-0
Bits 7 to 0: UART Receive Register (Read
Operations)/UART
Transmit
Register
(Write
Operations) (UR7/UT7 to UR0/UT0). This register is
used both as the UART transmit and receive buffer by the
host microcontroller. Received characters are always
read by the host microcontroller in direct convention,
meaning that if the CONV bit is 0, then characters
received using inverse convention are automatically
translated by the hardware. When the receive FIFO is
enabled, reads of URR always access the oldest avail-
able received data. For the synchronous mode of opera-
tion, the LSb (URR.0) reflects the state of the selected
card I/Ox line.
Writes by the host microcontroller to this register trans-
mit characters to the selected card. The host microcon-
troller should write data to UTR in direct convention
(inverse convention encoding is handled by the hard-
ware). The UTR register cannot be loaded during trans-
mission. The transmission:
Starts at the end of the write operation (rising edge
of WR) if the previous character has been transmit-
ted and the extra guard time has been satisfied.
Starts at the end of the extra guard time if that
guard time has not been satisfied.
Does not start if the transmission of the previous
character is not completed (e.g., during retransmis-
sion attempts or if a transmit parity error occurs).
For the synchronous mode of operation, only the LSb
(UTR.0) of the loaded data is transferred to the I/Ox pin
for the selected card.
Bit 7: Reserved.
Bits 6 to 4: Parity Error Count (PEC2 to PEC0). These
bits are used only for the T = 0 protocol to determine the
number of retransmission attempts that can occur in
transmit mode and the number of parity errors that can
occur before the PE bit is set to 1 to indicate that the par-
ity error limit has been reached. In transmit mode, the
DS8007A attempts to retransmit a character up to
(PEC2–PEC0) times (when NAK’d by the card) before
the PE bit is set. Retransmission attempts are automati-
cally made at 15 ETU from the previous start bit. If
PEC2–PEC0 = 000b, no retransmission attempt is made,
however, the host device can manually rewrite the char-
acter to UTR (in which case, it is re-sent as early as 13.5
ETU from the previous start bit of the error character).
In receive mode, if (PEC2–PEC0 + 1) parity errors have
been detected, the USR.PE bit is set to 1. For example,
if PEC2–PEC0 = 000b, only one parity error needs to be
detected for the PE bit to be set; if PEC2–PEC0 = 111b,
8 parity errors must be detected, etc. If a character is
correctly received before the allowed parity error count
is reached, the parity counter is reset. For the T = 1
protocol, the parity counter is not used. The PE bit is
set whenever a parity error is detected for a received
character.
Bit 3: FIFO Threshold Enable 1 (FTE1). When this bit
and the FTE0 (UCR1.7) bit are set, the programmable
FIFO threshold feature is enabled. This bit always reads
0 for compatibility.
Bits 2 to 0: FIFO Length (FL2 to FL0). These bits
determine the depth of the receive FIFO. The receive
FIFO has depth equal to (FL2–FL0) + 1 (e.g., FIFO
depth = 2 if FL2–FL0 = 001b).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS8007-ENG | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Multiprotocol Dual Smart Card Interface |
| DS8007-ENG+ | 功能描述:接口 - 專用 Multiprotocol Dual Smart Card Interface RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| DS8007-KIT | 功能描述:界面開發(fā)工具 DS8007 Eval Kit RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| DS8008-07 | 制造商:RICHTEK 制造商全稱:Richtek Technology Corporation 功能描述:2.5V to 5.5V Input Range |
| DS800SL-3 | 功能描述:線性和開關(guān)式電源 12V output 760W Gold w/ Reverse Air RoHS:否 制造商:TDK-Lambda 產(chǎn)品:Switching Supplies 開放式框架/封閉式:Enclosed 輸出功率額定值:800 W 輸入電壓:85 VAC to 265 VAC 輸出端數(shù)量:1 輸出電壓（通道 1）:20 V 輸出電流（通道 1）:40 A 商用/醫(yī)用: 輸出電壓（通道 2）: 輸出電流（通道 2）: 安裝風(fēng)格:Rack 長度: 寬度: 高度: |
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