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參數(shù)資料
| 型號： | DS7505U+T&R |
| 廠商： | Maxim Integrated |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 197K |
| 描述： | IC DGTL THERMOMETER 2WIRE 8-USOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 3,000 |
| 功能： | 溫度計，恒溫計 |
| 傳感器類型： | 內(nèi)部 |
| 感應溫度： | -55°C ~ 125°C |
| 精確度： | ±2°C（最小值） |
| 拓撲： | ADC（三角積分型），比較器，寄存器庫 |
| 輸出類型： | I²C?/SMBus? |
| 輸出警報： | 無 |
| 輸出風扇： | 無 |
| 電源電壓： | 1.7 V ~ 3.7 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應商設(shè)備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
General 2-Wire Information
" All data is transmitted MSB first over the 2-wire bus.
" One bit of data is transmitted on the 2-wire bus each
SCL period.
" A pullup resistor is required on the SDA line, and,
when the bus is idle, both SDA and SCL must remain
in a logic-high state.
" All bus communication must be initiated with a
START condition and terminated with a STOP condi-
tion. During a START or STOP is the only time SDA is
allowed to change states while SCL is high. At all
other times, changes on the SDA line can only occur
when SCL is low; SDA must remain stable when SCL
is high.
" After every 8-bit (1-byte) transfer, the receiving
device must answer with an ACK (or NACK), which
takes one SCL period. Therefore, nine clocks are
required for every 1-byte data transfer.
Writing to the DS7505: To write to the DS7505, the
master must generate a START followed by an address
byte containing the DS7505 bus address. The value of
the R/W bit must be a 0, which indicates that a write is
about to take place. The DS7505 responds with an
ACK after receiving the address byte. The master then
sends a pointer byte which tells the DS7505 which reg-
ister is being written to. The DS7505 again responds
with an ACK after receiving the pointer byte. Following
this ACK the master device must immediately begin
transmitting data to the DS7505. When writing to the
configuration register, the master must send one byte
of data (see Figure 9B), and when writing to the T
OS
or
T
HYST
registers the master must send two bytes of data
(see Figure 9C). After receiving each data byte, the
DS7505 responds with an ACK, and the transaction is
finished with a STOP from the master. All writes to the
DS7505 are made to shadow SRAM. Once data is writ-
ten to the shadow SRAM, it is only stored to EEPROM
by issuance of a Copy Data command from the master.
At that time, all registers are copied to EEPROM except
the Temperature register which is SRAM only.
Reading from the DS7505: When reading from the
DS7505, if the pointer was already pointed to the
desired register during a previous transaction, the read
can be performed immediately without changing the
pointer setting. In this case the master sends a START
followed by an address byte containing the DS7505
bus address. The R/W bit must be a 1, which tells the
DS7505 that a read is being performed. After the
DS7505 sends an ACK in response to the address
byte, the DS7505 begins transmitting the requested
data on the next clock cycle. When reading from the
configuration register, the DS7505 transmits one byte of
data, after which the master must respond with a NACK
followed by a STOP (see Figure 9E). For two-byte reads
(i.e., from the temperature, T
OS
or T
HYST
register), the
DS7505 transmits two bytes of data, and the master
must respond to the first data byte with an ACK and to
the second byte with a NACK followed by a STOP (see
Figure 9A). If only the most significant byte of data is
needed, the master can issue a NACK followed by a
STOP after reading the first data byte in which case the
transaction is the same as for a read from the configu-
ration register.
If the pointer is not already pointing to the desired reg-
ister, the pointer must first be updated as shown in
Figure 9D, which shows a pointer update followed by a
single-byte read. The value of the R/W bit in the initial
address byte is a 0 ( write ) since the master is going
to write a pointer byte to the DS7505. After the DS7505
responds to the address byte with an ACK, the master
sends a pointer byte that corresponds to the desired
register. The master must then perform a repeated start
followed by a standard one or two byte read sequence
(with R/W =1) as described in the previous paragraph.
The Recall Data command should be issued before a
read if assurance is needed that the contents of the
EEPROM in the Shadow SRAM when read.
Bus Timeout: The DS7505 has a bus timeout feature
that prevents communication errors from leaving the IC
in a state where SDA is held low disrupting other
devices on the bus. If the DS7505 holds the SDA line
low for a period of t
TIMEOUT
, its bus interface automati-
cally resets and release the SDA line. Bus communica-
tion frequency must be fast enough to prevent a reset
during normal operation. The bus timeout feature only
applies to when the DS7505 is holding SDA low. Other
devices can hold SDA low for an undefined period with-
out causing the interface to reset.
Command Set
Recall Data [B8h]
1011 1000
Refreshes SRAM shadow register with EEPROM data. It
is recommended that a Recall command be performed
before reading EEPROM-backed memory locations.
The master sends a START followed by an address
byte containing the DS7505 bus address. The R/W bit
must be a 0. The DS7505 responds with an ACK. If the
next byte is a 0xB8, the DS7505 recalls all EEPROM
data into shadow RAM locations.
Digital Thermometer and Thermostat
______________________________________________________________________________________ 11
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