參數(shù)資料
型號: DS5000FP-16+
廠商: Maxim Integrated Products
文件頁數(shù): 19/22頁
文件大小: 0K
描述: IC MODULE MICRO 16MHZ 80-QFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 66
系列: DS500x
核心處理器: 8051
芯體尺寸: 8-位
速度: 16MHz
連通性: EBI/EMI,SIO,UART/USART
外圍設(shè)備: 電源故障復(fù)位,WDT
輸入/輸出數(shù): 32
程序存儲器類型: SRAM
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4.75 V ~ 5.25 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 80-BQFP
包裝: 托盤
產(chǎn)品目錄頁面: 703 (CN2011-ZH PDF)
DS5000FP
6 of 22
INSTRUCTION SET
The DS5000FP executes an instruction set that is object code compatible with the industry standard 8051
microcontroller. As a result, software development packages such as assemblers and compilers that have
been written for the 8051 are compatible with the DS5000FP. A complete description of the instruction
set and operation are provided in the Secure Microcontroller User’s Guide.
Also note that the DS5000FP is embodied in the DS5000(T) and DS2250(T) modules. The DS5000(T)
combines the DS5000FP with one SRAM of either 8 or 32 kbytes and a lithium cell. An optional Real
Time Clock is also available in the DS5000T. This is packaged in a 40-pin DIP module. The DS2250(T)
is an identical function in a SIMM form factor. It also offers the option of a second 32k SRAM mapped
as data on Chip Enable 2.
MEMORY ORGANIZATION
Figure 2 illustrates the memory map accessed by the DS5000FP. The entire 64k of program and 64k of
data is available. The DS5000FP maps 32k of this space into the SRAM connected to the byte-wide bus.
This is the area from 0000h to 7FFFh (32k) and is reached via CE1 . Any area not mapped into the NV
RAM is reached via the Expanded bus on Ports 0 & 2. Selecting CE2 provides another 32k of potential
data storage. When CE2 is used, no data is available on the ports. The memory map is covered in detail in
the Secure Microcontroller User’s Guide.
Figure 3 illustrates a typical memory connection for a system using 8k bytes of SRAM. Figure 4 shows a
similar system with 32 kbytes. The byte-wide Address bus connects to the SRAM address lines. The bi-
directional byte-wide data bus connects the data I/O lines of the SRAM. CE1 provides the chip enable
and R/ W is the write enable. An additional RAM could be connected to CE2 , with common connections
for R/ W , BA14-0, and BD7-0.
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