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參數(shù)資料
| 型號： | DS4000N |
| 英文描述： | RECT BRIDGE 15A 100V WIRE LEADS |
| 中文描述： | 數(shù)控溫補 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 227K |
| 代理商： | DS4000N |
DS4000 Digitally Controlled TCXO
11 of 16
2-WIRE SERIAL INTERFACE
The DS4000 supports a bidirectional 2-wire serial bus and data transmission protocol. The bus must be controlled
by a master device, which generates the serial clock (SCL), controls the bus access, and generates the START
and STOP conditions. The DS4000 operates as a slave on the 2-wire bus. The DS4000 works in a regular mode
(100kHz clock rate) and a fast mode (400kHz clock rate), which are defined within the bus specifications.
Connections to the bus are made by the open-drain I/O signals SDA and SCL.
The following bus protocol has been defined (Figure 3):
Data transfer can be initiated only when the bus is not busy.
During data transfer, the data signal must remain stable whenever the clock signal is HIGH. Changes in the
data signal while the clock signal is HIGH are interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus Not Busy:
Both data and clock signals remain HIGH.
Start Data Transfer:
A change in the state of the data signal, from HIGH to LOW, while the clock line is HIGH,
defines the START condition.
Stop Data Transfer:
A change in the state of the data signal, from LOW to HIGH, while the clock line is HIGH,
defines the STOP condition.
Data Valid:
The state of the data signal represents valid data when, after a START condition, the data signal is
stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the
LOW period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions is not limited and is determined by the master device. The
information is transferred byte-wise and each receiver acknowledges with a ninth bit.
Acknowledge:
Each receiving device, when addressed, is required to generate an acknowledge after reception of
each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit.
A device that acknowledges must pull down the serial data (SDA) signal during the acknowledge clock pulse in
such a way that the SDA signal is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end-of-data to the slave by not
generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must
leave the data signal HIGH to enable the master to generate the STOP condition.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| DS4006B-DV | 制造商:Wiremold / Legrand 功能描述:DS4000 Half Seam Clip/Blank Faceplate Fitting, Fog White |
| DS400MH | 制造商:Eaton Corporation 功能描述:Safety Switch Access/Meyers Type Hub-4 Inch |
| DS4010A-DV | 制造商:Wiremold / Legrand 功能描述:DS4000 Entrance End Fitting, Fog White |
| DS4010B-DV | 制造商:Wiremold / Legrand 功能描述:DS4000 Blank End Fitting, Fog White |
| DS4017-DV | 制造商:Wiremold / Legrand 功能描述:DS4000 Internal Elbow Fitting, Fog White |
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