參數(shù)資料
型號(hào): DS3803
廠商: DALLAS SEMICONDUCTOR
元件分類: Static RAM
英文描述: 32K X 32 NON-VOLATILE SRAM MODULE, 70 ns, SMA72
封裝: SIMM-72
文件頁(yè)數(shù): 10/10頁(yè)
文件大小: 231K
代理商: DS3803
DS3803
9 of 10
3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. tDS is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or later than the WE low transition, the output
buffers remain in a high impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in a high impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high impedance state during this period.
9. Each DS3803 has a built-in switch that disconnects the lithium source until VCC is first applied by the
user. The expected tDR is defined as accumulative time in the absence of VCC starting from the time
power is first applied by the user.
10. In a power-down condition the voltage on any pin may not exceed the voltage on VCC.
11. tWR1, tDH1 are measured from WE going high.
12. tWR2, tDH2 are measured from CE going high.
DC TEST CONDITIONS
Outputs Open
Cycle = 200 ns
All Voltages are Referenced to Ground
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL gate
Input Pulse Levels: 0 - 3.0 V
Timing Measurements Reference Levels:
Input - 1.5V
Output - 1.5V
Input Pulse Rise and Fall Times: 5 ns
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