I2C Gamma and VCOM Buffer with EEP" />
參數(shù)資料
型號: DS3514T+
廠商: Maxim Integrated Products
文件頁數(shù): 15/21頁
文件大?。?/td> 0K
描述: IC I2C GAMMA/VCOM BUFF 48-TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 101
應(yīng)用: TFT-LCD 面板:伽瑪緩沖器,VCOM 驅(qū)動(dòng)器
輸出類型: 滿擺幅
電路數(shù): 14
電流 - 電源: 5mA
電流 - 輸出 / 通道: 4mA
電壓 - 電源,單路/雙路(±): 9 V ~ 15 V
安裝類型: 表面貼裝
封裝/外殼: 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-TQFN-EP(7x7)
包裝: 管件
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
DS3514
I2C Gamma and VCOM Buffer with EEPROM
_______________________________________________________________________________________
3
INPUT ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.7V to +5.5V, TA = -45°C to +95°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Resistance (GHH, GHM,
GLM, GLL)
75
k
Input Resistance Tolerance
TA= +25°C
-20
+20
%
Power-On Recall Voltage
VPOR
(Note 7)
1.6
2.6
V
Power-Up Time
tD
(Note 8)
25
ms
OUTPUT ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, VRL = +2.0V, GLL = +0.2V, GLM = +4.8V, GHM = +10.2V, VRH = +13.0V, GHH = +14.8V, TA = -45°C to
+95°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GM1–GM14 DAC Resolution
10
Bits
VCOM DAC Resolution
8
Bits
VCOM Integral Nonlinearity Error
INL
TA= +25°C (Note 9)
-0.5
+0.5
LSB
VCOM Differential Nonlinearity
Error
DNL
TA= +25°C (Note 10)
-0.5
+0.5
LSB
GM1–GM14 Integral
Nonlinearity Error
INL
TA= +25°C (Note 9)
-1.0
+1.0
LSB
GM1–GM14 Differential
Nonlinearity Error
DNL
TA= +25°C (Note 10)
-0.35
+0.35
LSB
Output Voltage Range (VCOM)
2.0
VDD - 2.0
V
Output Voltage Range (GM1–G14)
0.2
VDD - 0.2
V
VCOM Output Accuracy
TA= +25°C
-20
+20
mV
GM1–GM14 Offset
GM outputs = VDD/2, TA= +25°C
37
mV
GM1–GM14 Output Accuracy
GM outputs = VDD/2, TA= +25°C
-35
+35
mV
Voltage Gain (GM1–GM14)
0.995
V/V
Load Regulation
(VCOM, GM1–GM14)
1.0
mV/mA
Short-Circuit Current (VCOM)
To VDD or GND
250
mA
S0/S1 to LD Setup Time
tSU
Figure 2
37.5
ns
S0/S1 to LD Hold Time
tHD
Figure 2
37.5
ns
VCOM Settling Time from LD Low
to High (S0/S1 Meet tSU)
tSET-V
Settling to 0.1% of final VCOM level
(Figure 1) (Note 11)
2.0
μs
GM1–GM14 Settling Time from
LD Low to High
tSET-G
4tAU settled with ILOAD= ±20mA
(Figure 2) (Notes 11, 12, 13)
5.0
μs
S0, S1 to GM1–GM14 Output
10% Settled
tSEL
10% settling (Figure 3), LD = VCC
(asynchronous) (Notes 11, 13)
600
ns
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